Merge branch 'master' into riscv-types

Author: romancardenas

.github/workflows/changelog.yaml

@@ -19,6 +19,8 @@ jobs:
           filters: |
             riscv:
               - 'riscv/**'
+            riscv-macros:
+              - 'riscv-macros/**'
             riscv-pac:
               - 'riscv-pac/**'
             riscv-peripheral:
@@ -39,6 +41,14 @@ jobs:
           changeLogPath: ./riscv/CHANGELOG.md
           skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'
+      
+      - name: Check for CHANGELOG.md (riscv-macros)
+        if: steps.changes.outputs.riscv-macros == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: ./riscv-macros/CHANGELOG.md
+          skipLabels: 'skip changelog'
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-macros/CHANGELOG.md file.'
 
       - name: Check for CHANGELOG.md (riscv-pac)
         if: steps.changes.outputs.riscv-pac == 'true'

Cargo.toml

@@ -2,6 +2,7 @@
 resolver = "2"
 members = [
     "riscv",
+    "riscv-macros",
     "riscv-pac",
     "riscv-peripheral",
     "riscv-rt",
@@ -14,6 +15,7 @@ members = [
 
 default-members = [
     "riscv",
+    "riscv-macros",
     "riscv-pac",
     "riscv-peripheral",
     "riscv-rt",

LICENSE-APACHE.md

@@ -0,0 +1,201 @@
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+END OF TERMS AND CONDITIONS
+
+APPENDIX: How to apply the Apache License to your work.
+
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+Copyright [yyyy] [name of copyright owner]
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+you may not use this file except in compliance with the License.
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+
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LICENSE-MIT.md

@@ -0,0 +1,25 @@
+Copyright (c) 2018-2025  The Rust-Embedded Working Group
+
+Permission is hereby granted, free of charge, to any
+person obtaining a copy of this software and associated
+documentation files (the "Software"), to deal in the
+Software without restriction, including without
+limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of
+the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following
+conditions:
+
+The above copyright notice and this permission notice
+shall be included in all copies or substantial portions
+of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
+ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

riscv-macros/CHANGELOG.md

@@ -0,0 +1,21 @@
+# Change Log
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [Unreleased]
+
+### Added
+
+- New `rt` and `rt-v-trap` features to opt-in `riscv-rt`-related code in `riscv::pac_enum` macro.
+
+### Changed
+
+- Moved from `riscv/macros/` to `riscv-macros/`
+- Now, `riscv::pac_enum` macro only includes trap-related code if `rt` or `rt-v-trap` features are enabled.
+
+## [v0.3.0] - 2025-09-08
+
+This crate was placed inside `riscv/`. Check `riscv/CHANGELOG.md` for details

riscv/macros/Cargo.toml renamed to riscv-macros/Cargo.toml

@@ -4,7 +4,7 @@ authors = [
 ]
 categories = ["embedded", "no-std"]
 description = "Procedural macros re-exported in `riscv`"
-documentation = "https://docs.rs/riscv"
+documentation = "https://docs.rs/riscv-macros"
 keywords = ["riscv", "register", "peripheral"]
 license = "MIT OR Apache-2.0"
 name = "riscv-macros"

riscv-macros/README.md

@@ -0,0 +1,40 @@
+[![crates.io](https://img.shields.io/crates/d/riscv-macros.svg)](https://crates.io/crates/riscv-macros)
+[![crates.io](https://img.shields.io/crates/v/riscv-macros.svg)](https://crates.io/crates/riscv-macros)
+
+# `riscv-macros`
+
+> Procedural macros for the `riscv` crate.
+
+This project is developed and maintained by the [RISC-V team][team].
+
+## [Documentation](https://docs.rs/crate/riscv)
+
+## Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.61 and up. It *might*
+compile with older versions but that may change in any new patch release.
+
+## License
+
+Copyright 2024-2025 [RISC-V team][team]
+
+Permission to use, copy, modify, and/or distribute this software for any purpose
+with or without fee is hereby granted, provided that the above copyright notice
+and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
+FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
+OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
+THIS SOFTWARE.
+
+## Code of Conduct
+
+Contribution to this crate is organized under the terms of the [Rust Code of
+Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
+to intervene to uphold that code of conduct.
+
+[CoC]: ../CODE_OF_CONDUCT.md
+[team]: https://github.com/rust-embedded/wg#the-risc-v-team

riscv/macros/src/lib.rs renamed to riscv-macros/src/lib.rs

@@ -437,16 +437,14 @@ core::arch::global_asm!("
 ///     E3 = 3,
 /// }
 ///
-/// fn main() {
-///     assert_eq!(Exception::E1.number(), 1);
-///     assert_eq!(Exception::E3.number(), 3);
+/// assert_eq!(Exception::E1.number(), 1);
+/// assert_eq!(Exception::E3.number(), 3);
 ///
-///     assert_eq!(Exception::from_number(1), Ok(Exception::E1));
-///     assert_eq!(Exception::from_number(2), Err(2));
-///     assert_eq!(Exception::from_number(3), Ok(Exception::E3));
+/// assert_eq!(Exception::from_number(1), Ok(Exception::E1));
+/// assert_eq!(Exception::from_number(2), Err(2));
+/// assert_eq!(Exception::from_number(3), Ok(Exception::E3));
 ///
-///     assert_eq!(Exception::MAX_EXCEPTION_NUMBER, 3);
-/// }
+/// assert_eq!(Exception::MAX_EXCEPTION_NUMBER, 3);
 ///```
 #[proc_macro_attribute]
 pub fn pac_enum(attr: TokenStream, item: TokenStream) -> TokenStream {

riscv-pac/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Updated the license to `MIT or Apache-2.0`
+
 ## [v0.2.0] - 2024-10-19
 
 ### Added

riscv-pac/Cargo.toml

@@ -9,7 +9,7 @@ categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
 documentation = "https://docs.rs/riscv-pac"
 keywords = ["riscv", "register", "peripheral"]
-license = "ISC"
+license = "MIT OR Apache-2.0"
 
 [package.metadata.docs.rs]
 default-target = "riscv64imac-unknown-none-elf"