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1 parent 0eda3c5 commit 95c5234Copy full SHA for 95c5234
src/register/mip.rs
@@ -71,3 +71,30 @@ impl Mip {
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}
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read_csr_as!(Mip, 0x344, __read_mip);
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+set!(0x344, __set_mip);
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+clear!(0x344, __clear_mip);
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+
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+set_clear_csr!(
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+ /// User Software Interrupt Pending
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+ , set_usoft, clear_usoft, 1 << 0);
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+ /// Supervisor Software Interrupt Pending
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+ , set_ssoft, clear_ssoft, 1 << 1);
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+ /// Machine Software Interrupt Pending
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+ , set_msoft, clear_msoft, 1 << 3);
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+ /// User Timer Interrupt Pending
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+ , set_utimer, clear_utimer, 1 << 4);
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+ /// Supervisor Timer Interrupt Pending
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+ , set_stimer, clear_stimer, 1 << 5);
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+ /// Machine Timer Interrupt Pending
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+ , set_mtimer, clear_mtimer, 1 << 7);
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+ /// User External Interrupt Pending
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+ , set_uext, clear_uext, 1 << 8);
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+ /// Supervisor External Interrupt Pending
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+ , set_sext, clear_sext, 1 << 9);
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