riscv: make mcycle & minstret low bits writable

The RISC-V Instruction Set Manual Volume II: Privileged Architecture
20240411 specifies mcycle and minstret as "MRW" for read-write, instead
of "MRO" for read-only.

Author: hegza

riscv/src/register/mcycle.rs

@@ -1,4 +1,5 @@
 //! mcycle register
 
 read_csr_as_usize!(0xB00);
+write_csr_as_usize!(0xB00);
 read_composite_csr!(super::mcycleh::read(), read());

riscv/src/register/minstret.rs

@@ -1,4 +1,5 @@
 //! minstret register
 
 read_csr_as_usize!(0xB02);
+write_csr_as_usize!(0xB02);
 read_composite_csr!(super::minstreth::read(), read());