Merge #108

108: fix: clearify that mip.{MSIP, MTIP} are read-only r=almindor a=luojia65

closes #62

In RISC-V privileged specification, it says:

> Bits mip.MTIP and mie.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. MTIP is read-only in mip, and is cleared by writing to the memory-mapped machine-mode timer compare register.
>
> Bits mip.MSIP and mie.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. MSIP is read-only in mip, and is written by accesses to memory-mapped control registers, which are used by remote harts to provide machine-level interprocessor interrupts.

indicated by the specification, mip.MSIP and mip.MTIP bits are read-only. This pull request clearifies this by removing {set, clear}_{msoft, mtimer} functions from mip module of riscv crate.

Co-authored-by: luojia65 <[email protected]>

Author: bors[bot]

src/register/mip.rs

@@ -80,18 +80,12 @@ set_clear_csr!(
 set_clear_csr!(
     /// Supervisor Software Interrupt Pending
     , set_ssoft, clear_ssoft, 1 << 1);
-set_clear_csr!(
-    /// Machine Software Interrupt Pending
-    , set_msoft, clear_msoft, 1 << 3);
 set_clear_csr!(
     /// User Timer Interrupt Pending
     , set_utimer, clear_utimer, 1 << 4);
 set_clear_csr!(
     /// Supervisor Timer Interrupt Pending
     , set_stimer, clear_stimer, 1 << 5);
-set_clear_csr!(
-    /// Machine Timer Interrupt Pending
-    , set_mtimer, clear_mtimer, 1 << 7);
 set_clear_csr!(
     /// User External Interrupt Pending
     , set_uext, clear_uext, 1 << 8);