riscv: define satp CSR with macro helpers

Uses CSR macro helpers to define the `satp` CSR register.

Author: rmsyn

riscv/CHANGELOG.md

@@ -29,6 +29,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `mstatush` register
 - Use CSR helper macros to define `mtvec` register
 - Use CSR helper macros to define `mtvendorid` register
+- Use CSR helper macros to define `satp` register
 
 ## [v0.12.1] - 2024-10-20
 

riscv/src/register/satp.rs

@@ -2,144 +2,86 @@
 
 use crate::result::{Error, Result};
 
-/// satp register
-#[derive(Clone, Copy, Debug)]
-pub struct Satp {
-    bits: usize,
+read_write_csr! {
+    /// `satp` register
+    Satp: 0x180,
+    mask: usize::MAX,
 }
 
-impl Satp {
-    /// Returns the contents of the register as raw bits
-    #[inline]
-    pub fn bits(&self) -> usize {
-        self.bits
-    }
-
-    /// Current address-translation scheme
-    ///
-    /// **WARNING**: panics if the field has an invalid variant.
-    #[inline]
-    #[cfg(target_pointer_width = "32")]
-    pub fn mode(&self) -> Mode {
-        self.try_mode().unwrap()
-    }
-
-    /// Attempts to get the current address-translation scheme.
-    #[inline]
-    #[cfg(target_pointer_width = "32")]
-    pub fn try_mode(&self) -> Result<Mode> {
-        ((self.bits >> 31) as u8).try_into()
-    }
-
-    /// Current address-translation scheme
-    ///
-    /// **WARNING**: panics if the field has an invalid variant.
-    #[inline]
-    #[cfg(target_pointer_width = "64")]
-    pub fn mode(&self) -> Mode {
-        self.try_mode().unwrap()
-    }
-
-    /// Attempts to get the current address-translation scheme.
-    #[inline]
-    #[cfg(target_pointer_width = "64")]
-    pub fn try_mode(&self) -> Result<Mode> {
-        ((self.bits >> 60) as u8).try_into()
-    }
-
-    /// Address space identifier
-    #[inline]
-    #[cfg(target_pointer_width = "32")]
-    pub fn asid(&self) -> usize {
-        (self.bits >> 22) & 0x1FF // bits 22-30
+#[cfg(target_pointer_width = "32")]
+csr_field_enum! {
+    /// 32-bit satp mode
+    Mode {
+        default: Bare,
+        /// No translation or protection
+        Bare = 0,
+        /// Page-based 32-bit virtual addressing
+        Sv32 = 1,
     }
+}
 
-    /// Address space identifier
-    #[inline]
-    #[cfg(target_pointer_width = "64")]
-    pub fn asid(&self) -> usize {
-        (self.bits >> 44) & 0xFFFF // bits 44-59
+#[cfg(target_pointer_width = "64")]
+csr_field_enum! {
+    /// 64-bit satp mode
+    Mode {
+        default: Bare,
+        /// No translation or protection
+        Bare = 0,
+        /// Page-based 39-bit virtual addressing
+        Sv39 = 8,
+        /// Page-based 48-bit virtual addressing
+        Sv48 = 9,
+        /// Page-based 57-bit virtual addressing
+        Sv57 = 10,
+        /// Page-based 64-bit virtual addressing
+        Sv64 = 11,
     }
+}
 
+#[cfg(target_pointer_width = "32")]
+read_write_csr_field! {
+    Satp,
     /// Physical page number
-    #[inline]
-    #[cfg(target_pointer_width = "32")]
-    pub fn ppn(&self) -> usize {
-        self.bits & 0x3F_FFFF // bits 0-21
-    }
+    ppn: [0:21],
+}
 
+#[cfg(target_pointer_width = "64")]
+read_write_csr_field! {
+    Satp,
     /// Physical page number
-    #[inline]
-    #[cfg(target_pointer_width = "64")]
-    pub fn ppn(&self) -> usize {
-        self.bits & 0xFFF_FFFF_FFFF // bits 0-43
-    }
+    ppn: [0:43],
 }
 
-/// 32-bit satp mode
 #[cfg(target_pointer_width = "32")]
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-pub enum Mode {
-    /// No translation or protection
-    Bare = 0,
-    /// Page-based 32-bit virtual addressing
-    Sv32 = 1,
+read_write_csr_field! {
+    Satp,
+    /// Address space identifier
+    asid: [22:30],
 }
 
-/// 64-bit satp mode
 #[cfg(target_pointer_width = "64")]
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-pub enum Mode {
-    /// No translation or protection
-    Bare = 0,
-    /// Page-based 39-bit virtual addressing
-    Sv39 = 8,
-    /// Page-based 48-bit virtual addressing
-    Sv48 = 9,
-    /// Page-based 57-bit virtual addressing
-    Sv57 = 10,
-    /// Page-based 64-bit virtual addressing
-    Sv64 = 11,
+read_write_csr_field! {
+    Satp,
+    /// Address space identifier
+    asid: [44:59],
 }
 
 #[cfg(target_pointer_width = "32")]
-impl TryFrom<u8> for Mode {
-    type Error = Error;
-
-    fn try_from(val: u8) -> Result<Self> {
-        match val {
-            0 => Ok(Mode::Bare),
-            1 => Ok(Mode::Sv32),
-            _ => Err(Error::InvalidFieldVariant {
-                field: "mode",
-                value: val as usize,
-            }),
-        }
-    }
+read_write_csr_field! {
+    Satp,
+    /// Current address-translation scheme.
+    mode,
+    Mode: [31:31],
 }
 
 #[cfg(target_pointer_width = "64")]
-impl TryFrom<u8> for Mode {
-    type Error = Error;
-
-    fn try_from(val: u8) -> Result<Self> {
-        match val {
-            0 => Ok(Mode::Bare),
-            8 => Ok(Mode::Sv39),
-            9 => Ok(Mode::Sv48),
-            10 => Ok(Mode::Sv57),
-            11 => Ok(Mode::Sv64),
-            _ => Err(Error::InvalidFieldVariant {
-                field: "mode",
-                value: val as usize,
-            }),
-        }
-    }
+read_write_csr_field! {
+    Satp,
+    /// Current address-translation scheme.
+    mode,
+    Mode: [60:63],
 }
 
-read_csr_as!(Satp, 0x180);
-write_csr_as_usize!(0x180);
-
 /// Sets the register to corresponding page table mode, physical page number and address space id.
 ///
 /// **WARNING**: panics on: