Merge branch 'master' into add-peripheral

Author: romancardenas

.github/workflows/changelog.yaml

@@ -19,12 +19,14 @@ jobs:
           filters: |
             riscv:
               - 'riscv/**'
-            riscv-rt:
-              - 'riscv-rt/**'
             riscv-pac:
               - 'riscv-pac/**'
             riscv-peripheral:
               - 'riscv-peripheral/**'
+            riscv-rt:
+              - 'riscv-rt/**'
+            riscv-semihosting:
+              - 'riscv-semihosting/**'
 
       - name: Check for CHANGELOG.md (riscv)
         if: steps.changes.outputs.riscv == 'true'
@@ -34,6 +36,14 @@ jobs:
           skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'
 
+      - name: Check for CHANGELOG.md (riscv-pac)
+        if: steps.changes.outputs.riscv-pac == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: ./riscv-pac/CHANGELOG.md
+          skipLabels: 'skip changelog'
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-pac/CHANGELOG.md file.'
+      
       - name: Check for CHANGELOG.md (riscv-rt)
         if: steps.changes.outputs.riscv-rt == 'true'
         uses: dangoslen/changelog-enforcer@v3
@@ -42,14 +52,14 @@ jobs:
           skipLabels: 'skip changelog'
           missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-rt/CHANGELOG.md file.'
 
-      - name: Check for CHANGELOG.md (riscv-pac)
-        if: steps.changes.outputs.riscv-pac == 'true'
+      - name: Check for CHANGELOG.md (riscv-semihosting)
+        if: steps.changes.outputs.riscv-semihosting == 'true'
         uses: dangoslen/changelog-enforcer@v3
         with:
-          changeLogPath: ./riscv-pac/CHANGELOG.md
+          changeLogPath: ./riscv-semihosting/CHANGELOG.md
           skipLabels: 'skip changelog'
-          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-pac/CHANGELOG.md file.'
-      
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv-semihosting/CHANGELOG.md file.'
+
       - name: Check for CHANGELOG.md (riscv-peripheral)
         if: steps.changes.outputs.riscv-peripheral == 'true'
         uses: dangoslen/changelog-enforcer@v3

.github/workflows/riscv-rt.yaml

@@ -35,11 +35,11 @@ jobs:
           targets: ${{ matrix.target }}
       - name: Build (no features)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }}
-      - name : Build example (s-mode)
+      - name : Build (s-mode)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode
-      - name : Build example (single-hart)
+      - name : Build (single-hart)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart
-      - name: Build example (all features)
+      - name: Build (all features)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features
 
   # Job to check that all the builds succeeded

.github/workflows/riscv-semihosting.yaml

@@ -0,0 +1,63 @@
+on:
+  push:
+    branches: [ master ]
+  pull_request:
+  merge_group:
+
+name: Build check (riscv-semihosting)
+
+jobs:
+  # We check that the crate builds and links for all the toolchains and targets.
+  build-riscv:
+    strategy:
+      matrix:
+        # All generated code should be running on stable now, MRSV is 1.60.0
+        toolchain: [ stable, nightly, 1.60.0 ]
+        target:
+          - riscv32i-unknown-none-elf
+          - riscv32imc-unknown-none-elf
+          - riscv32imac-unknown-none-elf
+          - riscv64imac-unknown-none-elf
+          - riscv64gc-unknown-none-elf
+        include:
+          # Nightly is only for reference and allowed to fail
+          - toolchain: nightly
+            experimental: true
+    runs-on: ubuntu-latest
+    continue-on-error: ${{ matrix.experimental || false }}
+    steps:
+    - uses: actions/checkout@v4
+    - uses: dtolnay/rust-toolchain@master
+      with:
+        toolchain: ${{ matrix.toolchain }}
+        targets: ${{ matrix.target }}
+    - name: Build (M-mode)
+      run: cargo build --package riscv-semihosting --target ${{ matrix.target }}
+    - name: Build (U-mode)
+      run: cargo build --package riscv-semihosting --target ${{ matrix.target }} --features=u-mode
+    - name: Build (no semihosting)
+      run: cargo build --package riscv-semihosting --target ${{ matrix.target }} --features=no-semihosting
+
+  # On MacOS, Ubuntu, and Windows, we at least make sure that the crate builds and links.
+  build-others:
+    strategy:
+      matrix:
+        os: [ macos-latest, ubuntu-latest, windows-latest ]
+    runs-on: ${{ matrix.os }}
+    steps:
+      - uses: actions/checkout@v3
+      - uses: dtolnay/rust-toolchain@stable
+      - name: Build (no features)
+        run: cargo build --package riscv-semihosting
+      - name: Build (all features)
+        run: cargo build --package riscv-semihosting --all-features
+
+  # Job to check that all the builds succeeded
+  build-check:
+    needs:
+    - build-riscv
+    - build-others
+    runs-on: ubuntu-latest
+    if: always()
+    steps:
+      - run: jq --exit-status 'all(.result == "success")' <<< '${{ toJson(needs) }}'

.github/workflows/riscv.yaml

@@ -31,8 +31,12 @@ jobs:
       with:
         toolchain: ${{ matrix.toolchain }}
         targets: ${{ matrix.target }}
-    - name: Build (no features)
+    - name: Build (M-mode)
       run: cargo build --package riscv --target ${{ matrix.target }}
+    - name: Build (M-mode, critical section)
+      run: cargo build --package riscv --target ${{ matrix.target }} --features=critical-section-single-hart
+    - name: Build (S-mode)
+      run: cargo build --package riscv --target ${{ matrix.target }} --features=s-mode
     - name: Build (all features)
       run: cargo build --package riscv --target ${{ matrix.target }} --all-features
 

Cargo.toml

@@ -5,4 +5,5 @@ members = [
     "riscv-pac",
     "riscv-peripheral",
     "riscv-rt",
+    "riscv-semihosting",
 ]

README.md

@@ -6,7 +6,7 @@ This repository contains various crates useful for writing Rust programs on RISC
 * [`riscv-pac`]: Common traits to be implemented by RISC-V PACs
 * [`riscv-peripheral`]: Interfaces for standard RISC-V peripherals
 * [`riscv-rt`]: Startup code and interrupt handling
-
+* [`riscv-semihosting`]: Semihosting for RISC-V processors
 
 This project is developed and maintained by the [RISC-V team][team].
 
@@ -26,5 +26,6 @@ to intervene to uphold that code of conduct.
 [`riscv-pac`]: https://crates.io/crates/riscv-pac
 [`riscv-peripheral`]: https://crates.io/crates/riscv-peripheral
 [`riscv-rt`]: https://crates.io/crates/riscv-rt
+[`riscv-semihosting`]: https://crates.io/crates/riscv-semihosting
 [team]: https://github.com/rust-embedded/wg#the-risc-v-team
 [CoC]: CODE_OF_CONDUCT.md

riscv-rt/CHANGELOG.md

@@ -9,13 +9,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Add `links` field in `Cargo.toml`
+- Add FPU initialization
+- Static array for vectored-like handling of exceptions
 - New GitHub workflow for checking invalid labels in PRs
 - New GitHub workflow for checking modifications on CHANGELOG.md
 - New GitHub workflow for checking clippy lints in PRs
 - Optional cargo feature `single-hart` for single CPU targets
 
 ### Changed
 
+- Removed U-mode interrupts to align with latest RISC-V specification
+- Changed `Vector` union. Now, it uses `Option<fn>`, which is more idiomatic in Rust
 - Removed riscv-target dependency for build
 - Upgrade rust-version to 1.60
 - Cargo workspace for riscv and riscv-rt

riscv-rt/Cargo.toml

@@ -10,6 +10,7 @@ documentation = "https://docs.rs/riscv-rt"
 keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 edition = "2021"
+links = "riscv-rt" # Prevent multiple versions of riscv-rt being linked
 
 [features]
 s-mode = []

riscv-rt/build.rs

@@ -18,7 +18,7 @@ fn add_linker_script(arch_width: u32) -> io::Result<()> {
 }
 
 /// Parse the target RISC-V architecture and returns its bit width and the extension set
-fn parse_target(target: &str) -> (u32, HashSet<char>) {
+fn parse_target(target: &str, cargo_flags: &str) -> (u32, HashSet<char>) {
     // isolate bit width and extensions from the rest of the target information
     let arch = target
         .trim_start_matches("riscv")
@@ -43,18 +43,46 @@ fn parse_target(target: &str) -> (u32, HashSet<char>) {
         extensions.insert('d');
     }
 
+    let cargo_flags = cargo_flags
+        .split(0x1fu8 as char)
+        .filter(|arg| !arg.is_empty());
+
+    cargo_flags
+        .filter(|k| k.starts_with("target-feature="))
+        .flat_map(|str| {
+            let flags = str.split('=').collect::<Vec<&str>>()[1];
+            flags.split(',')
+        })
+        .for_each(|feature| {
+            let chars = feature.chars().collect::<Vec<char>>();
+            match chars[0] {
+                '+' => {
+                    extensions.insert(chars[1]);
+                }
+                '-' => {
+                    extensions.remove(&chars[1]);
+                }
+                _ => {
+                    panic!("Unsupported target feature operation");
+                }
+            }
+        });
+
     (bits, extensions)
 }
 
 fn main() {
     let target = env::var("TARGET").unwrap();
+    let cargo_flags = env::var("CARGO_ENCODED_RUSTFLAGS").unwrap();
     let _name = env::var("CARGO_PKG_NAME").unwrap();
 
     // set configuration flags depending on the target
     if target.starts_with("riscv") {
         println!("cargo:rustc-cfg=riscv");
 
-        let (bits, extensions) = parse_target(&target);
+        // This is required until target_arch & target_feature risc-v work is
+        // stable and in-use (rust 1.75.0)
+        let (bits, extensions) = parse_target(&target, &cargo_flags);
 
         // generate the linker script and expose the ISA width
         let arch_width = match bits {

riscv-rt/link.x.in

@@ -28,13 +28,25 @@ PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
-PROVIDE(UserSoft = DefaultHandler);
+PROVIDE(InstructionMisaligned = ExceptionHandler);
+PROVIDE(InstructionFault = ExceptionHandler);
+PROVIDE(IllegalInstruction = ExceptionHandler);
+PROVIDE(Breakpoint = ExceptionHandler);
+PROVIDE(LoadMisaligned = ExceptionHandler);
+PROVIDE(LoadFault = ExceptionHandler);
+PROVIDE(StoreMisaligned = ExceptionHandler);
+PROVIDE(StoreFault = ExceptionHandler);;
+PROVIDE(UserEnvCall = ExceptionHandler);
+PROVIDE(SupervisorEnvCall = ExceptionHandler);
+PROVIDE(MachineEnvCall = ExceptionHandler);
+PROVIDE(InstructionPageFault = ExceptionHandler);
+PROVIDE(LoadPageFault = ExceptionHandler);
+PROVIDE(StorePageFault = ExceptionHandler);
+
 PROVIDE(SupervisorSoft = DefaultHandler);
 PROVIDE(MachineSoft = DefaultHandler);
-PROVIDE(UserTimer = DefaultHandler);
 PROVIDE(SupervisorTimer = DefaultHandler);
 PROVIDE(MachineTimer = DefaultHandler);
-PROVIDE(UserExternal = DefaultHandler);
 PROVIDE(SupervisorExternal = DefaultHandler);
 PROVIDE(MachineExternal = DefaultHandler);