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Refactoring: use get_bit() instead of shifts
1 parent ab15a6a commit b665ade

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2 files changed

+22
-18
lines changed

2 files changed

+22
-18
lines changed

src/register/mie.rs

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
//! mie register
22
3+
use bit_field::BitField;
4+
35
/// mie register
46
#[derive(Clone, Copy, Debug)]
57
pub struct Mie {
@@ -16,55 +18,55 @@ impl Mie {
1618
/// User Software Interrupt Enable
1719
#[inline]
1820
pub fn usoft(&self) -> bool {
19-
self.bits & (1 << 0) == 1 << 0
21+
self.bits.get_bit(0)
2022
}
2123

2224
/// Supervisor Software Interrupt Enable
2325
#[inline]
2426
pub fn ssoft(&self) -> bool {
25-
self.bits & (1 << 1) == 1 << 1
27+
self.bits.get_bit(1)
2628
}
2729

2830
/// Machine Software Interrupt Enable
2931
#[inline]
3032
pub fn msoft(&self) -> bool {
31-
self.bits & (1 << 3) == 1 << 3
33+
self.bits.get_bit(3)
3234
}
3335

3436
/// User Timer Interrupt Enable
3537
#[inline]
3638
pub fn utimer(&self) -> bool {
37-
self.bits & (1 << 4) == 1 << 4
39+
self.bits.get_bit(4)
3840
}
3941

4042
/// Supervisor Timer Interrupt Enable
4143
#[inline]
4244
pub fn stimer(&self) -> bool {
43-
self.bits & (1 << 5) == 1 << 5
45+
self.bits.get_bit(5)
4446
}
4547

4648
/// Machine Timer Interrupt Enable
4749
#[inline]
4850
pub fn mtimer(&self) -> bool {
49-
self.bits & (1 << 7) == 1 << 7
51+
self.bits.get_bit(7)
5052
}
5153

5254
/// User External Interrupt Enable
5355
#[inline]
5456
pub fn uext(&self) -> bool {
55-
self.bits & (1 << 8) == 1 << 8
57+
self.bits.get_bit(8)
5658
}
5759

5860
/// Supervisor External Interrupt Enable
5961
#[inline]
6062
pub fn sext(&self) -> bool {
61-
self.bits & (1 << 9) == 1 << 9
63+
self.bits.get_bit(9)
6264
}
6365

6466
/// Machine External Interrupt Enable
6567
#[inline]
6668
pub fn mext(&self) -> bool {
67-
self.bits & (1 << 11) == 1 << 11
69+
self.bits.get_bit(11)
6870
}
6971
}
7072

src/register/mip.rs

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
//! mip register
22
3+
use bit_field::BitField;
4+
35
/// mip register
46
#[derive(Clone, Copy, Debug)]
57
pub struct Mip {
@@ -16,55 +18,55 @@ impl Mip {
1618
/// User Software Interrupt Pending
1719
#[inline]
1820
pub fn usoft(&self) -> bool {
19-
self.bits & (1 << 0) == 1 << 0
21+
self.bits.get_bit(0)
2022
}
2123

2224
/// Supervisor Software Interrupt Pending
2325
#[inline]
2426
pub fn ssoft(&self) -> bool {
25-
self.bits & (1 << 1) == 1 << 1
27+
self.bits.get_bit(1)
2628
}
2729

2830
/// Machine Software Interrupt Pending
2931
#[inline]
3032
pub fn msoft(&self) -> bool {
31-
self.bits & (1 << 3) == 1 << 3
33+
self.bits.get_bit(3)
3234
}
3335

3436
/// User Timer Interrupt Pending
3537
#[inline]
3638
pub fn utimer(&self) -> bool {
37-
self.bits & (1 << 4) == 1 << 4
39+
self.bits.get_bit(4)
3840
}
3941

4042
/// Supervisor Timer Interrupt Pending
4143
#[inline]
4244
pub fn stimer(&self) -> bool {
43-
self.bits & (1 << 5) == 1 << 5
45+
self.bits.get_bit(5)
4446
}
4547

4648
/// Machine Timer Interrupt Pending
4749
#[inline]
4850
pub fn mtimer(&self) -> bool {
49-
self.bits & (1 << 7) == 1 << 7
51+
self.bits.get_bit(7)
5052
}
5153

5254
/// User External Interrupt Pending
5355
#[inline]
5456
pub fn uext(&self) -> bool {
55-
self.bits & (1 << 8) == 1 << 8
57+
self.bits.get_bit(8)
5658
}
5759

5860
/// Supervisor External Interrupt Pending
5961
#[inline]
6062
pub fn sext(&self) -> bool {
61-
self.bits & (1 << 9) == 1 << 9
63+
self.bits.get_bit(9)
6264
}
6365

6466
/// Machine External Interrupt Pending
6567
#[inline]
6668
pub fn mext(&self) -> bool {
67-
self.bits & (1 << 11) == 1 << 11
69+
self.bits.get_bit(11)
6870
}
6971
}
7072

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