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1 parent 9d9cb77 commit b74b90bCopy full SHA for b74b90b
riscv/src/delay.rs
@@ -28,8 +28,8 @@ impl DelayNs for McycleDelay {
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#[inline]
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fn delay_ns(&mut self, ns: u32) {
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let t0 = mcycle::read64();
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- let us_64: u64 = ns.into();
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- let clock = (us_64 * (self.ticks_second as u64)) / 1_000_000_000u64;
+ let ns_64: u64 = ns.into();
+ let clock = (ns_64 * (self.ticks_second as u64)) / 1_000_000_000u64;
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while mcycle::read64().wrapping_sub(t0) <= clock {}
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}
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