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Adapt changelog entry
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riscv-rt/CHANGELOG.md

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@@ -13,7 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function.
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- Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the
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linker will place this new section in `REGION_BSS`.
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- Additional feature `no-mie-mip` to work on chips without the MIE and MIP CSRs (e.g. ESP32-C2, ESP32-C3)
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- Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3)
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### Changed
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