Transition to cargo workspace

Author: romancardenas

.github/workflows/changelog.yaml

@@ -1,4 +1,4 @@
-name: Check CHANGELOG.md
+name: Changelog check
 
 on:
   merge_group:
@@ -12,9 +12,18 @@ jobs:
       - name: Checkout code
         uses: actions/checkout@v4
 
-      - name: Check for CHANGELOG.md
+      - name: Check which component is modified 
+        uses: dorny/paths-filter@v2
+        id: changes
+        with:
+          filters: |
+            riscv:
+              - 'riscv/**'
+
+      - name: Check for CHANGELOG.md (riscv)
+        if: steps.changes.outputs.riscv == 'true'
         uses: dangoslen/changelog-enforcer@v3
         with:
+          changeLogPath: ./riscv/CHANGELOG.md
           skipLabels: 'skip changelog'
-          missingUpdateErrorMessage: 'Please add a changelog entry in the CHANGELOG.md file.'
-
+          missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'

Cargo.toml

@@ -1,26 +1,5 @@
-[package]
-name = "riscv"
-version = "0.10.1"
-edition = "2021"
-rust-version = "1.59"
-repository = "https://github.com/rust-embedded/riscv"
-authors = ["The RISC-V Team <[email protected]>"]
-categories = ["embedded", "hardware-support", "no-std"]
-description = "Low level access to RISC-V processors"
-keywords = ["riscv", "register", "peripheral"]
-license = "ISC"
-
-[package.metadata.docs.rs]
-all-features = true
-default-target = "riscv64imac-unknown-none-elf"
-targets = [
-    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
-    "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
+[workspace]
+resolver = "2"
+members = [
+    "riscv",
 ]
-
-[features]
-critical-section-single-hart = ["critical-section/restore-state-bool"]
-
-[dependencies]
-critical-section = "1.1.2"
-embedded-hal = "1.0.0-rc.1"

CHANGELOG.md renamed to riscv/CHANGELOG.md

@@ -0,0 +1,26 @@
+[package]
+name = "riscv"
+version = "0.10.1"
+edition = "2021"
+rust-version = "1.59"
+repository = "https://github.com/rust-embedded/riscv"
+authors = ["The RISC-V Team <[email protected]>"]
+categories = ["embedded", "hardware-support", "no-std"]
+description = "Low level access to RISC-V processors"
+keywords = ["riscv", "register", "peripheral"]
+license = "ISC"
+
+[package.metadata.docs.rs]
+all-features = true
+default-target = "riscv64imac-unknown-none-elf"
+targets = [
+    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
+    "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
+]
+
+[features]
+critical-section-single-hart = ["critical-section/restore-state-bool"]
+
+[dependencies]
+critical-section = "1.1.2"
+embedded-hal = "1.0.0-rc.1"