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romancardenasromancardenas
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Merge pull request #382 from KushalMeghani1644/update_qemu_ci
Move QEMU executables to a non-default member `test-qemu`, and add multi-hart tests
2 parents 29ef54b + 73f1a1c commit d0893ea

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-26
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14 files changed

+282
-26
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‎.github/workflows/qemu.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -32,9 +32,34 @@ jobs:
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qemu: riscv64
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- target: riscv64gc-unknown-none-elf
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qemu: riscv64
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example:
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- qemu_uart
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- qemu_semihosting
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example-features:
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- example: qemu_uart
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features: ""
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- example: qemu_semihosting
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features: ""
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- example: qemu_uart
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features: "s-mode"
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- example: multi_hart
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features: "multi-hart"
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exclude:
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# multi_hart requires atomics extension ('a'), exclude targets without it
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- example-features:
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example: multi_hart
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target-qemu:
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target: riscv32i-unknown-none-elf
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- example-features:
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example: multi_hart
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target-qemu:
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target: riscv32im-unknown-none-elf
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- example-features:
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example: multi_hart
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target-qemu:
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target: riscv32imc-unknown-none-elf
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# s-mode on riscv32 requires OpenSBI which has issues with some targets
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- example-features:
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features: "s-mode"
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target-qemu:
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qemu: riscv32
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steps:
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- name: Checkout
@@ -55,5 +80,9 @@ jobs:
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sudo apt install -y qemu-system-${{ matrix.target-qemu.qemu }}
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- name: Run-pass tests
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run: cargo run --package xtask -- qemu --target ${{ matrix.target-qemu.target }} --example ${{ matrix.example }}
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run: |
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if [ -n "${{ matrix.example-features.features }}" ]; then
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cargo run --package xtask -- qemu --target ${{ matrix.target-qemu.target }} --example ${{ matrix.example-features.example }} --features ${{ matrix.example-features.features }}
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else
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cargo run --package xtask -- qemu --target ${{ matrix.target-qemu.target }} --example ${{ matrix.example-features.example }}
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fi

‎Cargo.toml‎

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@@ -9,6 +9,7 @@ members = [
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"riscv-target-parser",
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"riscv-types",
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"tests-build",
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"tests-qemu",
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"tests-trybuild",
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"xtask",
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]

‎ci/expected/multi_hart.run‎

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@@ -0,0 +1,3 @@
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Hart 0: Initializing
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Hart 1: Running
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Hart 0: Both harts done

‎riscv-rt/CHANGELOG.md‎

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@@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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### Added
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- Moved QEMU test examples to dedicated `tests-qemu` crate with support for multiple configurations (m-mode, s-mode, single-hart, multi-hart)
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- Added examples for CI tests using semihosting and UART
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- New `no-mhartid` feature to load 0 to `a0` instead of reading `mhartid`.
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- New `no-xtvec` feature that removes interrupt stuff.

‎tests-qemu/Cargo.toml‎

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@@ -0,0 +1,18 @@
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[package]
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name = "tests-qemu"
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version = "0.1.0"
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edition = "2021"
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[build-dependencies]
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[dependencies]
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panic-halt = "1.0"
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riscv = { path = "../riscv" }
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riscv-rt = { path = "../riscv-rt" }
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riscv-semihosting = { path = "../riscv-semihosting" }
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[features]
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default = ["single-hart"]
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s-mode = ["riscv-rt/s-mode", "single-hart"]
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single-hart = ["riscv-rt/single-hart", "riscv/critical-section-single-hart"]
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multi-hart = []

‎tests-qemu/build.rs‎

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use std::{env, fs::File, io::Write, path::PathBuf};
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fn main() {
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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let s_mode = env::var_os("CARGO_FEATURE_S_MODE").is_some();
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let multi_hart = env::var_os("CARGO_FEATURE_MULTI_HART").is_some();
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// Multi-hart is only supported in M-mode; s-mode takes priority if both are enabled
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let memory_x = match (s_mode, multi_hart) {
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(true, _) => include_bytes!("memory-s-mode.x").as_slice(),
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(_, true) => include_bytes!("memory-multihart.x").as_slice(),
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_ => include_bytes!("memory.x").as_slice(),
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};
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File::create(out.join("memory.x"))
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.unwrap()
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.write_all(memory_x)
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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println!("cargo:rustc-link-arg=-Tmemory.x");
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println!("cargo:rerun-if-changed=memory.x");
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println!("cargo:rerun-if-changed=memory-multihart.x");
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println!("cargo:rerun-if-changed=memory-s-mode.x");
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println!("cargo:rerun-if-changed=build.rs");
28+
}

‎tests-qemu/examples/multi_hart.rs‎

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//! Multi-hart example demonstrating IPI-based hart synchronization.
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//!
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//! Hart 0 initializes UART and wakes Hart 1 via software interrupt (CLINT).
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//! Both harts print messages and synchronize before exit.
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#![no_std]
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#![no_main]
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9+
extern crate panic_halt;
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11+
use core::arch::global_asm;
12+
use core::sync::atomic::{AtomicBool, Ordering};
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use riscv_rt::entry;
14+
use riscv_semihosting::debug::{self, EXIT_SUCCESS};
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const UART_BASE: usize = 0x1000_0000;
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const UART_THR: usize = UART_BASE;
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const UART_LCR: usize = UART_BASE + 3;
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const UART_LSR: usize = UART_BASE + 5;
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const LCR_DLAB: u8 = 1 << 7;
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const LCR_8N1: u8 = 0x03;
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const LSR_THRE: u8 = 1 << 5;
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static UART_LOCK: AtomicBool = AtomicBool::new(false);
25+
static HART1_DONE: AtomicBool = AtomicBool::new(false);
26+
27+
fn uart_lock() {
28+
while UART_LOCK
29+
.compare_exchange(false, true, Ordering::Acquire, Ordering::Relaxed)
30+
.is_err()
31+
{
32+
core::hint::spin_loop();
33+
}
34+
}
35+
36+
fn uart_unlock() {
37+
UART_LOCK.store(false, Ordering::Release);
38+
}
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40+
unsafe fn uart_write_reg(off: usize, v: u8) {
41+
(off as *mut u8).write_volatile(v);
42+
}
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44+
unsafe fn uart_read_reg(off: usize) -> u8 {
45+
(off as *const u8).read_volatile()
46+
}
47+
48+
fn uart_init() {
49+
unsafe {
50+
uart_write_reg(UART_LCR, LCR_DLAB);
51+
uart_write_reg(UART_THR, 0x01);
52+
uart_write_reg(UART_BASE + 1, 0x00);
53+
uart_write_reg(UART_LCR, LCR_8N1);
54+
uart_write_reg(UART_BASE + 2, 0x07);
55+
}
56+
}
57+
58+
fn uart_write_byte(b: u8) {
59+
unsafe {
60+
while (uart_read_reg(UART_LSR) & LSR_THRE) == 0 {}
61+
uart_write_reg(UART_THR, b);
62+
}
63+
}
64+
65+
fn uart_print(s: &str) {
66+
uart_lock();
67+
for &b in s.as_bytes() {
68+
uart_write_byte(b);
69+
}
70+
uart_unlock();
71+
}
72+
73+
// Custom _mp_hook implementation in assembly
74+
// Hart 0 returns 1 (true) to initialize RAM
75+
// Hart 1 polls for IPI via CLINT, then returns 0 (false) to skip RAM init
76+
global_asm!(
77+
r#"
78+
.section .init.mp_hook, "ax"
79+
.global _mp_hook
80+
_mp_hook:
81+
beqz a0, 2f // if hart 0, return true
82+
83+
// Hart 1: Poll for IPI (no interrupts, just polling)
84+
// Clear any pending software interrupt first
85+
li t0, 0x02000004 // CLINT msip address for hart 1
86+
sw zero, 0(t0)
87+
88+
1: // Poll mip register for software interrupt pending
89+
csrr t0, mip
90+
andi t0, t0, 8 // Check MSIP bit
91+
beqz t0, 1b // If not set, keep polling
92+
93+
// Clear the software interrupt
94+
li t0, 0x02000004
95+
sw zero, 0(t0)
96+
97+
// Return false (0) - don't initialize RAM again
98+
li a0, 0
99+
ret
100+
101+
2: // Hart 0: return true to initialize RAM
102+
li a0, 1
103+
ret
104+
"#
105+
);
106+
107+
#[entry]
108+
fn main(hartid: usize) -> ! {
109+
if hartid == 0 {
110+
uart_init();
111+
uart_print("Hart 0: Initializing\n");
112+
113+
// Send IPI to Hart 1 (write to CLINT msip register for hart 1)
114+
unsafe {
115+
(0x02000004usize as *mut u32).write_volatile(1);
116+
}
117+
118+
while !HART1_DONE.load(Ordering::Acquire) {
119+
core::hint::spin_loop();
120+
}
121+
122+
uart_print("Hart 0: Both harts done\n");
123+
debug::exit(EXIT_SUCCESS);
124+
} else {
125+
// Hart 1 reaches here after _mp_hook detects IPI
126+
uart_print("Hart 1: Running\n");
127+
HART1_DONE.store(true, Ordering::Release);
128+
}
129+
130+
loop {
131+
core::hint::spin_loop();
132+
}
133+
}

riscv-rt/examples/qemu_semihosting.rs renamed to tests-qemu/examples/qemu_semihosting.rs

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@@ -2,7 +2,6 @@
22
//!
33
//! This example uses RISC-V semihosting to print output and cleanly exit QEMU.
44
//! Run with: `qemu-system-riscv32 -machine virt -nographic -semihosting-config enable=on,target=native -bios none -kernel <binary>`
5-
65
#![no_std]
76
#![no_main]
87

riscv-rt/examples/qemu_uart.rs renamed to tests-qemu/examples/qemu_uart.rs

File renamed without changes.

‎tests-qemu/memory-multihart.x‎

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1+
MEMORY
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{
3+
RAM : ORIGIN = 0x80000000, LENGTH = 16M
4+
}
5+
REGION_ALIAS("REGION_TEXT", RAM);
6+
REGION_ALIAS("REGION_RODATA", RAM);
7+
REGION_ALIAS("REGION_DATA", RAM);
8+
REGION_ALIAS("REGION_BSS", RAM);
9+
REGION_ALIAS("REGION_HEAP", RAM);
10+
REGION_ALIAS("REGION_STACK", RAM);
11+
_max_hart_id = 1;
12+
INCLUDE link.x

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