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1 parent a6cc40c commit e3dcd0bCopy full SHA for e3dcd0b
riscv/src/register/mseccfg.rs
@@ -92,3 +92,27 @@ read_write_csr_field! {
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pmm,
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PMM: [32:33],
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}
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+
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+#[cfg(test)]
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+mod tests {
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+ use super::*;
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+ #[test]
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+ fn test_mseccfg() {
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+ let mut mseccfg = Mseccfg::from_bits(0);
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+ test_csr_field!(mseccfg, mml);
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+ test_csr_field!(mseccfg, mmwp);
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+ test_csr_field!(mseccfg, rlb);
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+ test_csr_field!(mseccfg, useed);
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+ test_csr_field!(mseccfg, sseed);
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+ test_csr_field!(mseccfg, mlpe);
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+ #[cfg(not(target_arch = "riscv32"))]
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+ {
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+ test_csr_field!(mseccfg, pmm: PMM::Disabled);
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+ test_csr_field!(mseccfg, pmm: PMM::EnabledXlen57);
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+ test_csr_field!(mseccfg, pmm: PMM::EnabledXlen48);
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+ }
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+}
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