Merge #104

104: SBI mode r=almindor a=pgraubner

Introducing Supervisor Binary Interface (SBI) compatibility as a build-time feature. Main goal is to allow riscv-rt based implementations to be bootstrapped by a SBI-firmware (like in `qemu-system-riscv64`).

* Introduce compiler switches for assembly in order to switch between machine mode / supervisor mode
* Introduce cargo feature for conditional compilation
* Patch lib.rs for supervisor-mode compatibility

The only interface this PR is braking is `mp_hook`, which needs a mhartid replacement for smode. The hart id is passed by the caller.
Tested with `qemu-system-riscv64`.

See also documentation/features/sbi for further implementation details.

Co-authored-by: Pablo Graubner <[email protected]>

Author: bors[bot]

riscv-rt/CHANGELOG.md

@@ -10,6 +10,9 @@ keywords = ["riscv", "runtime", "startup"]
 license = "ISC"
 edition = "2018"
 
+[features]
+s-mode = []
+
 [dependencies]
 r0 = "1.0.0"
 riscv = "0.8"

riscv-rt/Cargo.toml

@@ -46,8 +46,14 @@ _abs_start:
     .cfi_startproc
     .cfi_undefined ra
 
+    #ifdef SMODE
+    csrw sie, 0     // interrupt disable 
+    csrw sip, 0     // no pending interrupts
+    #else
     csrw mie, 0
     csrw mip, 0
+    #endif
+    
 
     li  x1, 0
     li  x2, 0
@@ -84,8 +90,13 @@ _abs_start:
     la gp, __global_pointer$
     .option pop
 
-    // Check hart id
+    #ifdef SMODE
+    // there is no equivalent of mhartid in supervisor mode.
+    // instead, the hartid is passed as paramter by SMODE
+    mv t2, a0   
+    #else 
     csrr t2, mhartid
+    #endif
     lui t0, %hi(_max_hart_id)
     add t0, t0, %lo(_max_hart_id)
     bgtu t2, t0, abort
@@ -165,7 +176,11 @@ default_start_trap:
     LOAD a7, 15*REGBYTES(sp)
 
     addi sp, sp, 16*REGBYTES
+    #ifdef SMODE
+    sret
+    #else
     mret
+    #endif
 
 /* Make sure there is an abort when linking */
 .section .text.abort

riscv-rt/asm.S

@@ -31,6 +31,14 @@ do
 
     riscv64-unknown-elf-gcc -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
     riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf.a bin/$crate.o
+
+    #s-mode
+    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=ilp32${abi} -march=rv32${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv32${ext}-unknown-none-elf-smode.a bin/$crate.o
+
+    riscv64-unknown-elf-gcc -DSMODE -ggdb3 -fdebug-prefix-map=$(pwd)=/riscv-rt -c -mabi=lp64${abi} -march=rv64${ext} asm.S -o bin/$crate.o
+    riscv64-unknown-elf-ar crs bin/riscv64${ext}-unknown-none-elf-smode.a bin/$crate.o
+
 done
 
 rm bin/$crate.o