Merge #48

48: Release v0.7.0 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <[email protected]>

Author: bors[bot]

riscv-rt/CHANGELOG.md

@@ -0,0 +1,31 @@
+# Change Log
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [Unreleased]
+
+## [v0.7.0] - 2020-03-10
+
+### Added
+
+- Assure address of PC at startup
+- Implement interrupt and exception handling
+- Add support for the `riscv32i-unknown-none-elf` target
+- Added Changelog
+
+### Fixed
+
+- Fix linker script compatibility with GNU linker
+
+### Changed
+
+- Move `abort` out of the `.init` section
+- Update `r0` to v1.0.0
+- Set MSRV to 1.38
+
+
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.0...HEAD
+[v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0

riscv-rt/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.6.1"
+version = "0.7.0"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "no-std"]