diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 67a37179..24845e1b 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -12,6 +12,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Add `miselect` CSR - Improved assembly macro handling in asm.rs +### Fixed + +- Fixed `riscv::pac_enum` macro. Now, it only generates `riscv-rt`-related code if feature `rt` + is enabled in the caller crate (presumably, a PAC). + ## [v0.15.0] - 2025-09-08 ### Added diff --git a/riscv/macros/src/lib.rs b/riscv/macros/src/lib.rs index 5f4bf8f3..7ca5535d 100644 --- a/riscv/macros/src/lib.rs +++ b/riscv/macros/src/lib.rs @@ -280,7 +280,7 @@ impl PacEnumItem { }; let mut asm = format!( r#" -#[cfg(all(feature = "v-trap", any(target_arch = "riscv32", target_arch = "riscv64")))] +#[cfg(all(feature = "rt", feature = "v-trap", any(target_arch = "riscv32", target_arch = "riscv64")))] core::arch::global_asm!(" .section .trap.vector, \"ax\" .global _vector_table @@ -366,8 +366,8 @@ core::arch::global_asm!(" let handlers = self.handlers(&trap_config); let interrupt_array = self.handlers_array(); let cfg_v_trap = match is_core_interrupt { - true => Some(quote!(#[cfg(not(feature = "v-trap"))])), - false => None, + true => quote!(#[cfg(all(feature = "rt", not(feature = "v-trap")))]), + false => quote!(#[cfg(feature = "rt")]), }; // Push the interrupt handler functions and the interrupt array diff --git a/tests-build/Cargo.toml b/tests-build/Cargo.toml index 4798fa37..7c604461 100644 --- a/tests-build/Cargo.toml +++ b/tests-build/Cargo.toml @@ -9,6 +9,7 @@ riscv = { path = "../riscv" } riscv-rt = { path = "../riscv-rt" } [features] +rt = [] pre-init = ["riscv-rt/pre-init"] single-hart = ["riscv-rt/single-hart"] v-trap = ["riscv-rt/v-trap"] diff --git a/tests-trybuild/Cargo.toml b/tests-trybuild/Cargo.toml index 40270009..71bdd733 100644 --- a/tests-trybuild/Cargo.toml +++ b/tests-trybuild/Cargo.toml @@ -9,4 +9,5 @@ riscv-rt = { path = "../riscv-rt", features = ["no-exceptions", "no-interrupts", trybuild = "1.0" [features] +rt = [] v-trap = ["riscv-rt/v-trap"]