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Default to the case of register read-write access when read-only and
write-only fields are mixed.
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src/lib.rs

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -109,11 +109,8 @@ pub fn gen_register(r: &Register, d: &Defaults) -> Vec<Tokens> {
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Access::ReadOnly
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} else if fields.iter().all(|f| f.access == Some(Access::WriteOnly)) {
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Access::WriteOnly
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} else if fields.iter().any(|f| f.access == Some(Access::ReadWrite)) {
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Access::ReadWrite
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} else {
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panic!("unexpected case: {:#?}",
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fields.iter().map(|f| f.access).collect::<Vec<_>>())
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Access::ReadWrite
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}
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});
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