Skip to content

Commit 99dde35

Browse files
committed
non variant field repr
1 parent 62eee7b commit 99dde35

File tree

2 files changed

+3
-7
lines changed

2 files changed

+3
-7
lines changed

CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
1010
- Fix new `mismatched-lifetime-syntaxes` lint warnings
1111
- Adapt RISC-V specific codegen for `riscv-peripheral` v0.3.0 rework
1212
- Include `riscv-peripheral` peripherals in `Peripherals` struct
13+
- `repr(transparent)` for field wrapper
1314
- Ensure `__INTERRUPTS` are `#[no_mangle]` on Xtensa.
1415
- Add `base_isa` field to `riscv_config` to allow the `riscv_rt::core_interrupt`
1516
macro to properly generate start trap assembly routines in vectored mode.

src/generate/register.rs

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1497,12 +1497,6 @@ fn add_with_no_variants(
14971497
.as_ref()
14981498
.map(|feature| quote!(#[cfg_attr(feature = #feature, derive(defmt::Format))]));
14991499

1500-
let cast = if fty == "bool" {
1501-
quote! { val.0 as u8 != 0 }
1502-
} else {
1503-
quote! { val.0 as _ }
1504-
};
1505-
15061500
let desc = if let Some(rv) = reset_value {
15071501
format!("{desc}\n\nValue on reset: {rv}")
15081502
} else {
@@ -1513,11 +1507,12 @@ fn add_with_no_variants(
15131507
#[doc = #desc]
15141508
#defmt
15151509
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1510+
#[repr(transparent)]
15161511
pub struct #pc(#fty);
15171512
impl From<#pc> for #fty {
15181513
#[inline(always)]
15191514
fn from(val: #pc) -> Self {
1520-
#cast
1515+
val.0
15211516
}
15221517
}
15231518
});

0 commit comments

Comments
 (0)