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src/lib.rs

Lines changed: 30 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -223,29 +223,40 @@
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//! /// Inter-integrated circuit
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//! pub mod i2c1 {
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//! /// Register block
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//! #[repr(C)]
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//! pub struct RegisterBlock {
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//! cr1: CR1,
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//! cr2: CR2,
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//! oar1: OAR1,
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//! oar2: OAR2,
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//! dr: DR,
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//! }
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//! impl RegisterBlock {
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//! /// 0x00 - Control register 1
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//! pub cr1: CR1,
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//! #[inline(always)]
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//! pub const fn cr1(&self) -> &CR1 {
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//! &self.cr1
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//! }
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//! /// 0x04 - Control register 2
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//! pub cr2: CR2,
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//! #[inline(always)]
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//! pub const fn cr2(&self) -> &CR2 {
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//! &self.cr2
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//! }
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//! /// 0x08 - Own address register 1
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//! pub oar1: OAR1,
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//! /// 0x0c - Own address register 2
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//! pub oar2: OAR2,
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//! /// 0x10 - Timing register
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//! pub timingr: TIMINGR,
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//! /// Status register 1
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//! pub timeoutr: TIMEOUTR,
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//! /// Interrupt and Status register
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//! pub isr: ISR,
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//! /// 0x1c - Interrupt clear register
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//! pub icr: ICR,
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//! /// 0x20 - PEC register
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//! pub pecr: PECR,
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//! /// 0x24 - Receive data register
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//! pub rxdr: RXDR,
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//! /// 0x28 - Transmit data register
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//! pub txdr: TXDR,
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//! #[inline(always)]
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//! pub const fn oar1(&self) -> &OAR1 {
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//! &self.oar1
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//! }
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//! #[doc = "0x0c - Own address register 2"]
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//! #[inline(always)]
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//! pub const fn oar2(&self) -> &OAR2 {
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//! &self.oar2
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//! }
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//! #[doc = "0x10 - Data register"]
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//! #[inline(always)]
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//! pub const fn dr(&self) -> &DR {
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//! &self.dr
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//! }
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//! }
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//! }
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//! ```

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