rm reg_sizes

Author: burrbull

CHANGELOG.md

@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Make `generic.rs` generic
 - Change initial write value for registers with modifiedWriteValues
 - Update `clap` to 4.0, use `irx-config` instead of `clap_conf`
 - Add #[must_use] to prevent hanging field writers

src/generate/device.rs

@@ -7,7 +7,7 @@ use std::borrow::Cow;
 use std::fs::File;
 use std::io::Write;
 
-use crate::util::{self, Config, ToSanitizedCase, U32Ext};
+use crate::util::{self, Config, ToSanitizedCase};
 use crate::Target;
 use anyhow::{Context, Result};
 
@@ -146,15 +146,10 @@ pub fn render(d: &Device, config: &Config, device_x: &mut String) -> Result<Toke
         });
     }
 
-    let reg_sizes = util::get_register_sizes(d);
-
     let generic_file = std::str::from_utf8(include_bytes!("generic.rs"))?;
     if config.generic_mod {
         let mut file = File::create(config.output_dir.join("generic.rs"))?;
         writeln!(file, "{}", generic_file)?;
-        for ty in reg_sizes {
-            writeln!(file, "impl_proxy!({});", ty.size_to_str()?)?;
-        }
         if config.target == Target::Msp430 && config.nightly {
             let msp430_atomic_file =
                 std::str::from_utf8(include_bytes!("generic_msp430_atomic.rs"))?;
@@ -175,10 +170,6 @@ pub fn render(d: &Device, config: &Config, device_x: &mut String) -> Result<Toke
         }
     } else {
         let mut tokens = syn::parse_file(generic_file)?.into_token_stream();
-        for ty in reg_sizes {
-            let ty = Ident::new(ty.size_to_str()?, Span::call_site());
-            tokens.extend(quote! { impl_proxy!(#ty); });
-        }
         if config.target == Target::Msp430 && config.nightly {
             let msp430_atomic_file =
                 std::str::from_utf8(include_bytes!("generic_msp430_atomic.rs"))?;

src/generate/generic.rs

@@ -1,5 +1,6 @@
 use core::marker;
 
+/// Raw register type (`u8`, `u16`, `u32`, ...)
 pub trait RawReg:
     Copy
     + Default
@@ -8,7 +9,9 @@ pub trait RawReg:
     + core::ops::Not<Output = Self>
     + core::ops::Shl<u8, Output = Self>
 {
+    /// Mask for bits of width `WI`
     fn mask<const WI: u8>() -> Self;
+    /// Mask for bits of width 1
     fn one() -> Self;
 }
 
@@ -549,6 +552,7 @@ where
         unsafe { self.bits(variant.into()) }
     }
 }
+
 impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,
@@ -569,13 +573,15 @@ where
         self.bits(variant.into())
     }
 }
+
 impl_bit_proxy!(BitWriter);
 impl_bit_proxy!(BitWriter1S);
 impl_bit_proxy!(BitWriter0C);
 impl_bit_proxy!(BitWriter1C);
 impl_bit_proxy!(BitWriter0S);
 impl_bit_proxy!(BitWriter1T);
 impl_bit_proxy!(BitWriter0T);
+
 impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,
@@ -594,6 +600,7 @@ where
         self.bit(false)
     }
 }
+
 impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,
@@ -607,6 +614,7 @@ where
         self.bit(true)
     }
 }
+
 impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,
@@ -620,6 +628,7 @@ where
         self.bit(false)
     }
 }
+
 impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,
@@ -633,6 +642,7 @@ where
         self.bit(true)
     }
 }
+
 impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,
@@ -646,6 +656,7 @@ where
         self.bit(false)
     }
 }
+
 impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,
@@ -659,6 +670,7 @@ where
         self.bit(true)
     }
 }
+
 impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF>
 where
     REG: Writable + RegisterSpec<Ux = U>,

src/util.rs

@@ -545,20 +545,6 @@ pub fn build_rs() -> TokenStream {
     }
 }
 
-pub fn get_register_sizes(d: &Device) -> Vec<u32> {
-    let mut reg_sizes = HashSet::new();
-    for p in &d.peripherals {
-        for r in p.all_registers() {
-            if let Some(size) = r.properties.size {
-                reg_sizes.insert(size);
-            }
-        }
-    }
-    let mut reg_sizes: Vec<_> = reg_sizes.into_iter().collect();
-    reg_sizes.sort();
-    reg_sizes
-}
-
 pub trait FullName {
     fn fullname(&self, ignore_group: bool) -> Cow<str>;
 }