diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index b85cb520..1c56f42d 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -144,8 +144,7 @@ jobs:
           - { chip: MKW22D5 }
           - { chip: MK02F12810 }
           # Silicon Labs
-          # TODO: fix doc rendering bug when math `>` is present in description
-          #- { chip: SIM3L1x8_SVD }
+          - { chip: SIM3L1x8_SVD }
           # Nordic chips
           - { chip: nrf51, options: "-- -f register_mod::s:_mod" }
           - { chip: nrf52, options: "-- -f register_mod::s:_mod" }
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 157948d7..110b0c25 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -20,6 +20,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
 - Update `svd-rs` to 0.14.11
 - Added `#![cfg_attr(docsrs, feature(doc_auto_cfg))]` to the generated library code. This
   adds a display of the feature gates in the documentation of the generated library
+- Split on the start of attribute instead of the end
 
 ## [v0.35.0] - 2024-11-12
 
diff --git a/src/main.rs b/src/main.rs
index d1dc1f4a..d3efbeba 100755
--- a/src/main.rs
+++ b/src/main.rs
@@ -353,7 +353,7 @@ Ignore this option if you are not building your own FPGA based soft-cores."),
     let filename = if config.make_mod { "mod.rs" } else { "lib.rs" };
     let mut file = File::create(path.join(filename)).expect("Couldn't create output file");
 
-    let data = items.to_string().replace("] ", "]\n");
+    let data = items.to_string().replace(" # [", "\n#[");
     file.write_all(data.as_ref())
         .expect("Could not write code to lib.rs");