From 58e10d75f5579ab9d1d73195038a201538460d0c Mon Sep 17 00:00:00 2001
From: Andrey Zgarbul <zgarbul.andrey@gmail.com>
Date: Sun, 23 Nov 2025 12:11:05 +0300
Subject: [PATCH] set_bits/clear_bits

---
 src/generate/generic.rs | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/generate/generic.rs b/src/generate/generic.rs
index e527a4a8..f6c46600 100644
--- a/src/generate/generic.rs
+++ b/src/generate/generic.rs
@@ -291,6 +291,16 @@ impl<REG: Writable> W<REG> {
         self.bits = bits;
         self
     }
+    #[inline(always)]
+    pub unsafe fn set_bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits |= bits;
+        self
+    }
+    #[inline(always)]
+    pub unsafe fn clear_bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits &= !bits;
+        self
+    }
 }
 impl<REG> W<REG>
 where
@@ -424,6 +434,18 @@ where
         self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
         self.w
     }
+
+    #[inline(always)]
+    pub unsafe fn set_bits(self, value: FI::Ux) -> &'a mut W<REG> {
+        self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
+        self.w
+    }
+
+    #[inline(always)]
+    pub unsafe fn clear_bits(self, value: FI::Ux) -> &'a mut W<REG> {
+        self.w.bits &= !((REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o);
+        self.w
+    }
 }
 
 impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>