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avr: implement __[u]divmod(h|q)i4
GCC uses a special calling convention for integer multiplication and devision. ref: https://gcc.gnu.org/wiki/avr-gcc#Exceptions_to_the_Calling_Convention Unless we teach the compiler about this convention we're limited to implementing these functions via naked_asm!. The implementations provided here derive from libcc. ref: https://github.com/gcc-mirror/gcc/blob/95f10974a9190e345776604480a2df0191104308/libgcc/config/avr/lib1funcs.S
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‎compiler-builtins/src/int/udiv.rs‎

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@@ -43,6 +43,144 @@ intrinsics! {
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((rem as u64) << 32) | (div as u64)
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}
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/// Returns unsigned 8-bit `n / d` and `n % d`.
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///
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/// Note: GCC implements a [non-standard calling convention](https://gcc.gnu.org/wiki/avr-gcc#Exceptions_to_the_Calling_Convention) for this function.
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#[naked]
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pub unsafe extern "C" fn __udivmodqi4() {
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// Derived from: https://github.com/gcc-mirror/gcc/blob/95f10974a9190e345776604480a2df0191104308/libgcc/config/avr/lib1funcs.S#L1365
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// r25: remainder
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// r24: dividend, quotient
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// r22: divisor
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// r23: loop counter
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core::arch::naked_asm!(
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"clr r25", // clear remainder
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"ldi r23, 8", // init loop counter
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"lsl r24", // shift dividend
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"rol r25", // shift dividend into remainder
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"cp r25, r22", // compare remainder & divisor
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"brcs 2", // remainder <= divisor
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"sub r25, r22", // restore remainder
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"rol r24", // shift dividend (with CARRY)
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"dec r23", // decrement loop counter
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"brne -14",
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"com r24", // complement result (C flag was complemented in loop)
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"ret",
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);
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}
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/// Returns signed 8-bit `n / d` and `n % d`.
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///
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/// Note: GCC implements a [non-standard calling convention](https://gcc.gnu.org/wiki/avr-gcc#Exceptions_to_the_Calling_Convention) for this function.
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#[naked]
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pub unsafe extern "C" fn __divmodqi4() {
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// Derived from: https://github.com/gcc-mirror/gcc/blob/95f10974a9190e345776604480a2df0191104308/libgcc/config/avr/lib1funcs.S#L1385
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// r25: remainder
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// r24: dividend, quotient
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// r22: divisor
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// r23: loop counter
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core::arch::naked_asm!(
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"bst r24, 7", // store sign of dividend
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"mov r0, r24",
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"eor r0, r22", // r0.7 is sign of result
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"sbrc r24, 7",
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"neg r24", // dividend negative : negate
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"sbrc r22, 7",
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"neg r22", // divisor negative : negate
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// TODO: "call" => instruction requires a CPU feature not currently enabled
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// TODO: gcc checks for __AVR_HAVE_JMP_CALL__
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"rcall __udivmodqi4", // do the unsigned div/mod
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"brtc 2",
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"neg r25", // correct remainder sign
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"sbrc r0,7",
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"neg r24", // correct result sign
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"ret",
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);
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}
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/// Returns unsigned 16-bit `n / d` and `n % d`.
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///
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/// Note: GCC implements a [non-standard calling convention](https://gcc.gnu.org/wiki/avr-gcc#Exceptions_to_the_Calling_Convention) for this function.
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#[naked]
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pub unsafe extern "C" fn __udivmodhi4() {
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// Derived from: https://github.com/gcc-mirror/gcc/blob/95f10974a9190e345776604480a2df0191104308/libgcc/config/avr/lib1funcs.S#L1427
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// r26: remainder (low)
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// r27: remainder (high)
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// r24: dividend (low)
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// r25: dividend (high)
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// r22: divisor (low)
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// r23: divisor (high)
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// r21: loop counter
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core::arch::naked_asm!(
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"sub r26, r26",
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"sub r27, r27", // clear remainder and carry
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"ldi r21, 17", // init loop counter
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"rjmp .+14", // jump to entry point
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"rol r26", // shift dividend into remainder
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"rol r27",
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"cp r26, r22", // compare remainder & divisor
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"cpc r27, r23",
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"brcs .+4", // remainder < divisor
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"sub r26, r22", // restore remainder
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"sbc r27, r23",
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"rol r24", // shift dividend (with CARRY)
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"rol r25",
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"dec r21", // decrement loop counter
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"brne .-22",
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"com r24",
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"com r25",
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// TODO: "movw" => instruction requires a CPU feature not currently enabled
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// TODO: gcc checks for __AVR_HAVE_MOVW__
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"mov r22, r24",
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"mov r23, r25",
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"mov r24, r26",
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"mov r25, r27",
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"ret",
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);
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}
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/// Returns signed 16-bit `n / d` and `n % d`.
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///
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/// Note: GCC implements a [non-standard calling convention](https://gcc.gnu.org/wiki/avr-gcc#Exceptions_to_the_Calling_Convention) for this function.
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#[naked]
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pub unsafe extern "C" fn __divmodhi4() {
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// Derived from: https://github.com/gcc-mirror/gcc/blob/95f10974a9190e345776604480a2df0191104308/libgcc/config/avr/lib1funcs.S#L1457
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// r26: remainder (low)
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// r27: remainder (high)
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// r24: dividend (low)
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// r25: dividend (high)
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// r22: divisor (low)
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// r23: divisor (high)
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// r21: loop counter
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core::arch::naked_asm!(
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"bst r25, 7", // store sign of dividend
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"mov r0, r23",
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"brtc .+4",
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"com r0", // r0.7 is sign of result
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"rcall .+12", // dividend negative : negate
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"sbrc r23, 7",
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"rcall .+16", // divisor negative : negate
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// TODO: "call" => instruction requires a CPU feature not currently enabled
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// TODO: gcc checks for __AVR_HAVE_JMP_CALL__
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"rcall __udivmodhi4", // do the unsigned div/mod
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"sbrc r0, 7",
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"rcall .+10", // correct remainder sign
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"brtc .+14",
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"com r25", // correct dividend/remainder sign
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"neg r24",
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"sbci r25, 0xFF",
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"ret",
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"com r23", // correct divisor/result sign
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"neg r22",
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"sbci r23, 0xFF",
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"ret",
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);
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}
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}
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intrinsics! {

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