Skip to content

Commit 1d12f89

Browse files
authored
Merge pull request #4523 from Stypox/data-race-tracing
Add tracing to data race functions
2 parents cf97d7d + ca431f2 commit 1d12f89

File tree

1 file changed

+6
-0
lines changed

1 file changed

+6
-0
lines changed

src/machine.rs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1394,6 +1394,7 @@ impl<'tcx> Machine<'tcx> for MiriMachine<'tcx> {
13941394
GlobalDataRaceHandler::Genmc(genmc_ctx) =>
13951395
genmc_ctx.memory_load(machine, ptr.addr(), range.size)?,
13961396
GlobalDataRaceHandler::Vclocks(_data_race) => {
1397+
let _trace = enter_trace_span!(data_race::before_memory_read);
13971398
let AllocDataRaceHandler::Vclocks(data_race, weak_memory) = &alloc_extra.data_race
13981399
else {
13991400
unreachable!();
@@ -1429,6 +1430,7 @@ impl<'tcx> Machine<'tcx> for MiriMachine<'tcx> {
14291430
genmc_ctx.memory_store(machine, ptr.addr(), range.size)?;
14301431
}
14311432
GlobalDataRaceHandler::Vclocks(_global_state) => {
1433+
let _trace = enter_trace_span!(data_race::before_memory_write);
14321434
let AllocDataRaceHandler::Vclocks(data_race, weak_memory) =
14331435
&mut alloc_extra.data_race
14341436
else {
@@ -1465,6 +1467,7 @@ impl<'tcx> Machine<'tcx> for MiriMachine<'tcx> {
14651467
GlobalDataRaceHandler::Genmc(genmc_ctx) =>
14661468
genmc_ctx.handle_dealloc(machine, ptr.addr(), size, align, kind)?,
14671469
GlobalDataRaceHandler::Vclocks(_global_state) => {
1470+
let _trace = enter_trace_span!(data_race::before_memory_deallocation);
14681471
let data_race = alloc_extra.data_race.as_vclocks_mut().unwrap();
14691472
data_race.write(
14701473
alloc_id,
@@ -1675,6 +1678,7 @@ impl<'tcx> Machine<'tcx> for MiriMachine<'tcx> {
16751678
local: mir::Local,
16761679
) -> InterpResult<'tcx> {
16771680
if let Some(data_race) = &frame.extra.data_race {
1681+
let _trace = enter_trace_span!(data_race::after_local_read);
16781682
data_race.local_read(local, &ecx.machine);
16791683
}
16801684
interp_ok(())
@@ -1686,6 +1690,7 @@ impl<'tcx> Machine<'tcx> for MiriMachine<'tcx> {
16861690
storage_live: bool,
16871691
) -> InterpResult<'tcx> {
16881692
if let Some(data_race) = &ecx.frame().extra.data_race {
1693+
let _trace = enter_trace_span!(data_race::after_local_write);
16891694
data_race.local_write(local, storage_live, &ecx.machine);
16901695
}
16911696
interp_ok(())
@@ -1708,6 +1713,7 @@ impl<'tcx> Machine<'tcx> for MiriMachine<'tcx> {
17081713
if let Some(data_race) =
17091714
&machine.threads.active_thread_stack().last().unwrap().extra.data_race
17101715
{
1716+
let _trace = enter_trace_span!(data_race::after_local_moved_to_memory);
17111717
data_race.local_moved_to_memory(
17121718
local,
17131719
alloc_info.data_race.as_vclocks_mut().unwrap(),

0 commit comments

Comments
 (0)