@@ -483,7 +483,7 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
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fn apply_events ( & mut self , events : crate :: shims:: trace:: MemEvents ) -> InterpResult < ' tcx > {
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let this = self . eval_context_mut ( ) ;
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//let accesses = events.accesses;
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- let handle = this. machine . alloc_addresses . borrow ( ) ;
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+ /* let handle = this.machine.alloc_addresses.borrow();
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for id in &handle.exposed {
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let &base_addr = handle.base_addr.get(id).unwrap();
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let info = this.get_alloc_info(*id);
@@ -497,13 +497,22 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
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if info.mutbl.is_not() && acc_kind.did_write() {
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throw_ub_format!(""); // TODO: fill this in lol
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}
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-
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- if acc_kind. did_write ( ) {
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+ if acc_kind.did_read() {
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+ let src = Pointer::from_addr_invalid(*acc_base);
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+ this.read_immediate_raw(&src);
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+ self.expose_provenance(provenance)
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+ }
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+
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+ if acc_kind.did_write() {
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+ //let alloc = self.alloc_id_from_addr(addr, size, only_exposed_allocations)
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}
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}
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}
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- }
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+ }*/
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+ /*for (acc_base, acc_len, acc_kind) in &events.accesses {
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+ let alloc_id = self.alloc_id_from_addr(addr, size, only_exposed_allocations)
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+ }*/
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interp_ok ( ( ) )
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}
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