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1 parent fbfe15c commit d1b06f1Copy full SHA for d1b06f1
src/intrinsics/simd.rs
@@ -1,7 +1,7 @@
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use rand::Rng;
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use rustc_apfloat::Float;
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-use rustc_middle::ty::FloatTy;
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use rustc_middle::ty;
+use rustc_middle::ty::FloatTy;
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use super::check_intrinsic_arg_count;
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use crate::helpers::{ToHost, ToSoft};
@@ -79,7 +79,7 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
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}
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FloatTy::F128 => unimplemented!("f16_f128"),
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};
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-
+
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this.write_scalar(val, &dest)?;
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