Remove illegal space.

Sorry, I'm the useless-details sheriff.

Author: thethomasboyer

src/atomics.md

@@ -96,8 +96,8 @@ However there's a third potential state that the hardware enables:
 * `y = 2`: (thread 2 saw `x = 1`, but not `y = 3`, and then overwrote `y = 3`)
 
 It's worth noting that different kinds of CPU provide different guarantees. It
-is common to separate hardware into two categories: strongly-ordered and weakly-
-ordered. Most notably x86/64 provides strong ordering guarantees, while ARM
+is common to separate hardware into two categories: strongly-ordered and weakly-ordered.
+Most notably x86/64 provides strong ordering guarantees, while ARM
 provides weak ordering guarantees. This has two consequences for concurrent
 programming: