Fix cg_clif implementation

Author: sayantn

compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs

@@ -27,8 +27,8 @@ use rustc_span::{Symbol, sym};
 
 pub(crate) use self::llvm::codegen_llvm_intrinsic_call;
 use crate::cast::clif_intcast;
-use crate::codegen_f16_f128;
 use crate::prelude::*;
+use crate::{codegen_f16_f128, common};
 
 fn bug_on_incorrect_arg_count(intrinsic: impl std::fmt::Display) -> ! {
     bug!("wrong number of args for intrinsic {}", intrinsic);
@@ -659,27 +659,26 @@ fn codegen_regular_intrinsic_call<'tcx>(
             intrinsic_args!(fx, args => (x, y, z); intrinsic);
             let layout = x.layout();
 
-            let width_bits = layout.size.bits() as u64;
-            let width_bits = fx.bcx.ins().iconst(types::I32, width_bits as i64);
+            let width_bits = layout.size.bits() as i64;
 
             let lhs_bits = x.load_scalar(fx);
             let rhs_bits = y.load_scalar(fx);
             let raw_shift_bits = z.load_scalar(fx);
 
             let ty = fx.bcx.func.dfg.value_type(lhs_bits);
-            let zero = fx.bcx.ins().iconst(ty, 0);
+            let zero = common::type_zero_value(fx.bcx, ty);
 
-            let shift_bits = fx.bcx.ins().urem(raw_shift_bits, width_bits);
+            let shift_bits = fx.bcx.ins().band_imm(raw_shift_bits, width_bits - 1);
 
             // lhs_bits << shift_bits
             let shl = fx.bcx.ins().ishl(lhs_bits, shift_bits);
 
-            let inv_shift_bits = fx.bcx.ins().isub(width_bits, shift_bits);
+            let inv_shift_bits = fx.bcx.ins().irsub_imm(shift_bits, width_bits);
 
-            // rhs_bits.bounded_shr(inv_shift_bits)
-            let inv_shift_bits_mod = fx.bcx.ins().urem(inv_shift_bits, width_bits);
+            // rhs_bits.unbounded_shr(inv_shift_bits)
+            let inv_shift_bits_mod = fx.bcx.ins().band_imm(inv_shift_bits, width_bits - 1);
             let shr = fx.bcx.ins().ushr(rhs_bits, inv_shift_bits_mod);
-            let is_zero = fx.bcx.ins().icmp(IntCC::Equal, inv_shift_bits_mod, zero);
+            let is_zero = fx.bcx.ins().icmp_imm(IntCC::Equal, shift_bits, 0);
             let shr = fx.bcx.ins().select(is_zero, zero, shr);
 
             let res = fx.bcx.ins().bor(shr, shl);
@@ -689,27 +688,26 @@ fn codegen_regular_intrinsic_call<'tcx>(
             intrinsic_args!(fx, args => (x, y, z); intrinsic);
             let layout = x.layout();
 
-            let width_bits = layout.size.bits() as u64;
-            let width_bits = fx.bcx.ins().iconst(types::I32, width_bits as i64);
+            let width_bits = layout.size.bits() as i64;
 
             let lhs_bits = x.load_scalar(fx);
             let rhs_bits = y.load_scalar(fx);
             let raw_shift_bits = z.load_scalar(fx);
 
             let ty = fx.bcx.func.dfg.value_type(lhs_bits);
-            let zero = fx.bcx.ins().iconst(ty, 0);
+            let zero = common::type_zero_value(fx.bcx, ty);
 
-            let shift_bits = fx.bcx.ins().urem(raw_shift_bits, width_bits);
+            let shift_bits = fx.bcx.ins().band_imm(raw_shift_bits, width_bits - 1);
 
             // rhs_bits >> shift_bits
             let shr = fx.bcx.ins().ushr(rhs_bits, shift_bits);
 
-            let inv_shift_bits = fx.bcx.ins().isub(width_bits, shift_bits);
+            let inv_shift_bits = fx.bcx.ins().irsub_imm(shift_bits, width_bits);
 
-            // lhs_bits.bounded_shl(inv_shift_bits)
-            let inv_shift_bits_mod = fx.bcx.ins().urem(inv_shift_bits, width_bits);
+            // lhs_bits.unbounded_shl(inv_shift_bits)
+            let inv_shift_bits_mod = fx.bcx.ins().band_imm(inv_shift_bits, width_bits - 1);
             let shl = fx.bcx.ins().ishl(lhs_bits, inv_shift_bits_mod);
-            let is_zero = fx.bcx.ins().icmp(IntCC::Equal, inv_shift_bits_mod, zero);
+            let is_zero = fx.bcx.ins().icmp_imm(IntCC::Equal, shift_bits, 0);
             let shl = fx.bcx.ins().select(is_zero, zero, shl);
 
             let res = fx.bcx.ins().bor(shr, shl);