Implement ppc/ppc64 preserves_flags option for inline asm

Treat cr0 and xer as implicitly clobbered flags if preserves_flags
is not specified. cr0 is commonly used, and xer can be tricky as
it is modified by some shift operations. These are both caller-save
in all ABIs, so neglicting to specify preserves_flags should have
little overhead in cases where it could, but is not set.

fpscr and vscr are not tracked as they contain sticky bits
which are generally assumed to be volatile, but do not contains flags
used to control branches.

Author: pmur

compiler/rustc_codegen_gcc/src/asm.rs

@@ -546,9 +546,26 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
         }
 
         if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
-            // TODO(@Commeownist): I'm not 100% sure this one clobber is sufficient
-            // on all architectures. For instance, what about FP stack?
-            extended_asm.add_clobber("cc");
+            match asm_arch {
+                InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {
+                    let clobbers = ["cr0", "xer"];
+                    clobbers.into_iter().for_each(|x| extended_asm.add_clobber(x));
+                }
+                _ => {
+                    // The machine specific flag preservation should be consistent across codegen
+                    // backends.
+                    //
+                    // gcc documents "cc" as being supported by all targets, but what flags are
+                    // clobbered is architecture specific. On many targets, this has no effect.
+                    // See documentation for target specific details.
+                    //
+                    // https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Clobbers-and-Scratch-Registers
+                    //
+                    // At the time of commenting, cc is only documented as having an effect on
+                    // x86/arm/aarch64/s390.
+                    extended_asm.add_clobber("cc");
+                }
+            }
         }
         if !options.contains(InlineAsmOptions::NOMEM) {
             extended_asm.add_clobber("memory");

compiler/rustc_codegen_llvm/src/asm.rs

@@ -251,7 +251,9 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
                     constraints.push("~{sreg}".to_string());
                 }
                 InlineAsmArch::Nvptx64 => {}
-                InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {}
+                InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {
+                    constraints.extend_from_slice(&["~{cr0}".to_string(), "~{xer}".to_string()]);
+                }
                 InlineAsmArch::Hexagon => {}
                 InlineAsmArch::LoongArch32 | InlineAsmArch::LoongArch64 => {
                     constraints.extend_from_slice(&[

src/doc/unstable-book/src/language-features/asm-experimental-arch.md

@@ -201,6 +201,9 @@ These flags registers must be restored upon exiting the asm block if the `preser
   - The status register `r2`.
 - M68k
   - The condition code register `ccr`.
+- PowerPC
+  - The condition register `cr0`
+  - The fixed-point exception register `xer`
 - SPARC
   - Integer condition codes (`icc` and `xcc`)
   - Floating-point condition codes (`fcc[0-3]`)

tests/codegen-llvm/asm/powerpc-clobbers.rs

@@ -77,3 +77,28 @@ pub unsafe fn vs32_clobber() {
 pub unsafe fn clobber_abi() {
     asm!("", clobber_abi("C"), options(nostack, nomem, preserves_flags));
 }
+
+// CHECK-LABEL: @clobber_no_preserves_flags
+// CHECK: call void asm sideeffect "", "~{cr0},~{xer}"()
+#[no_mangle]
+pub unsafe fn clobber_no_preserves_flags() {
+    asm!("", options(nostack, nomem));
+}
+
+// CHECK-LABEL: @clobber_preservesflags
+// CHECK: call void asm sideeffect "", "~{memory}"()
+#[no_mangle]
+pub unsafe fn clobber_preservesflags() {
+    asm!("", options(nostack, preserves_flags));
+}
+
+// Output format depends on the availability of altivec and vsx
+// CHECK-LABEL: @clobber_abi_no_preserves_flags
+#[no_mangle]
+// powerpc: asm sideeffect "", "={r0},={r3},={r4},={r5},={r6},={r7},={r8},={r9},={r10},={r11},={r12},={f0},={f1},={f2},={f3},={f4},={f5},={f6},={f7},={f8},={f9},={f10},={f11},={f12},={f13},~{vs0},~{vs1},~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~{vs7},~{vs8},~{vs9},~{vs10},~{vs11},~{vs12},~{vs13},~{vs14},~{vs15},~{vs16},~{vs17},~{vs18},~{vs19},~{vs20},~{vs21},~{vs22},~{vs23},~{vs24},~{vs25},~{vs26},~{vs27},~{vs28},~{vs29},~{vs30},~{vs31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{cr0},~{cr1},~{cr5},~{cr6},~{cr7},~{ctr},~{lr},~{xer},~{cr0},~{xer}"()
+// powerpc64: asm sideeffect "", "={r0},={r3},={r4},={r5},={r6},={r7},={r8},={r9},={r10},={r11},={r12},={f0},={f1},={f2},={f3},={f4},={f5},={f6},={f7},={f8},={f9},={f10},={f11},={f12},={f13},={v0},={v1},={v2},={v3},={v4},={v5},={v6},={v7},={v8},={v9},={v10},={v11},={v12},={v13},={v14},={v15},={v16},={v17},={v18},={v19},~{vs0},~{vs1},~{vs2},~{vs3},~{vs4},~{vs5},~{vs6},~{vs7},~{vs8},~{vs9},~{vs10},~{vs11},~{vs12},~{vs13},~{vs14},~{vs15},~{vs16},~{vs17},~{vs18},~{vs19},~{vs20},~{vs21},~{vs22},~{vs23},~{vs24},~{vs25},~{vs26},~{vs27},~{vs28},~{vs29},~{vs30},~{vs31},~{cr0},~{cr1},~{cr5},~{cr6},~{cr7},~{ctr},~{lr},~{xer},~{cr0},~{xer}"()
+// powerpc64le: asm sideeffect "", "={r0},={r3},={r4},={r5},={r6},={r7},={r8},={r9},={r10},={r11},={r12},={f0},={f1},={f2},={f3},={f4},={f5},={f6},={f7},={f8},={f9},={f10},={f11},={f12},={f13},={vs0},={vs1},={vs2},={vs3},={vs4},={vs5},={vs6},={vs7},={vs8},={vs9},={vs10},={vs11},={vs12},={vs13},={vs14},={vs15},={vs16},={vs17},={vs18},={vs19},={vs20},={vs21},={vs22},={vs23},={vs24},={vs25},={vs26},={vs27},={vs28},={vs29},={vs30},={vs31},={v0},={v1},={v2},={v3},={v4},={v5},={v6},={v7},={v8},={v9},={v10},={v11},={v12},={v13},={v14},={v15},={v16},={v17},={v18},={v19},~{cr0},~{cr1},~{cr5},~{cr6},~{cr7},~{ctr},~{lr},~{xer},~{cr0},~{xer}"()
+// aix64: asm sideeffect "", "={r0},={r3},={r4},={r5},={r6},={r7},={r8},={r9},={r10},={r11},={r12},={f0},={f1},={f2},={f3},={f4},={f5},={f6},={f7},={f8},={f9},={f10},={f11},={f12},={f13},={vs0},={vs1},={vs2},={vs3},={vs4},={vs5},={vs6},={vs7},={vs8},={vs9},={vs10},={vs11},={vs12},={vs13},={vs14},={vs15},={vs16},={vs17},={vs18},={vs19},={vs20},={vs21},={vs22},={vs23},={vs24},={vs25},={vs26},={vs27},={vs28},={vs29},={vs30},={vs31},={v0},={v1},={v2},={v3},={v4},={v5},={v6},={v7},={v8},={v9},={v10},={v11},={v12},={v13},={v14},={v15},={v16},={v17},={v18},={v19},~{cr0},~{cr1},~{cr5},~{cr6},~{cr7},~{ctr},~{lr},~{xer},~{cr0},~{xer}"()
+pub unsafe fn clobber_abi_no_preserves_flags() {
+    asm!("", clobber_abi("C"), options(nostack, nomem));
+}