Add RISC-V target features

Author: Amanieu

src/librustc_codegen_llvm/llvm_util.rs

@@ -236,6 +236,15 @@ const POWERPC_WHITELIST: &[(&str, Option<Symbol>)] = &[
 const MIPS_WHITELIST: &[(&str, Option<Symbol>)] =
     &[("fp64", Some(sym::mips_target_feature)), ("msa", Some(sym::mips_target_feature))];
 
+const RISCV_WHITELIST: &[(&str, Option<Symbol>)] = &[
+    ("m", Some(sym::riscv_target_feature)),
+    ("a", Some(sym::riscv_target_feature)),
+    ("c", Some(sym::riscv_target_feature)),
+    ("f", Some(sym::riscv_target_feature)),
+    ("d", Some(sym::riscv_target_feature)),
+    ("e", Some(sym::riscv_target_feature)),
+];
+
 const WASM_WHITELIST: &[(&str, Option<Symbol>)] =
     &[("simd128", Some(sym::wasm_target_feature)), ("atomics", Some(sym::wasm_target_feature))];
 
@@ -253,6 +262,7 @@ pub fn all_known_features() -> impl Iterator<Item = (&'static str, Option<Symbol
         .chain(HEXAGON_WHITELIST.iter().cloned())
         .chain(POWERPC_WHITELIST.iter().cloned())
         .chain(MIPS_WHITELIST.iter().cloned())
+        .chain(RISCV_WHITELIST.iter().cloned())
         .chain(WASM_WHITELIST.iter().cloned())
 }
 
@@ -297,6 +307,7 @@ pub fn target_feature_whitelist(sess: &Session) -> &'static [(&'static str, Opti
         "hexagon" => HEXAGON_WHITELIST,
         "mips" | "mips64" => MIPS_WHITELIST,
         "powerpc" | "powerpc64" => POWERPC_WHITELIST,
+        "riscv32" | "riscv64" => RISCV_WHITELIST,
         "wasm32" => WASM_WHITELIST,
         _ => &[],
     }

src/librustc_feature/active.rs

@@ -228,6 +228,7 @@ declare_features! (
     (active, hexagon_target_feature, "1.27.0", Some(44839), None),
     (active, powerpc_target_feature, "1.27.0", Some(44839), None),
     (active, mips_target_feature, "1.27.0", Some(44839), None),
+    (active, riscv_target_feature, "1.27.0", Some(44839), None),
     (active, avx512_target_feature, "1.27.0", Some(44839), None),
     (active, mmx_target_feature, "1.27.0", Some(44839), None),
     (active, sse4a_target_feature, "1.27.0", Some(44839), None),

src/librustc_span/symbol.rs

@@ -607,6 +607,7 @@ symbols! {
         Result,
         Return,
         rhs,
+        riscv_target_feature,
         rlib,
         rotate_left,
         rotate_right,

src/librustc_typeck/collect.rs

@@ -2278,6 +2278,7 @@ fn from_target_feature(
                 Some(sym::hexagon_target_feature) => rust_features.hexagon_target_feature,
                 Some(sym::powerpc_target_feature) => rust_features.powerpc_target_feature,
                 Some(sym::mips_target_feature) => rust_features.mips_target_feature,
+                Some(sym::riscv_target_feature) => rust_features.riscv_target_feature,
                 Some(sym::avx512_target_feature) => rust_features.avx512_target_feature,
                 Some(sym::mmx_target_feature) => rust_features.mmx_target_feature,
                 Some(sym::sse4a_target_feature) => rust_features.sse4a_target_feature,

src/test/ui/target-feature/gate.rs

@@ -25,6 +25,7 @@
 // gate-test-movbe_target_feature
 // gate-test-rtm_target_feature
 // gate-test-f16c_target_feature
+// gate-test-riscv_target_feature
 
 #[target_feature(enable = "avx512bw")]
 //~^ ERROR: currently unstable