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bjorn3bjorn3
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Move a couple of macros to intrinsics::simd
1 parent 4e3a8d5 commit 8ace43e

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+115
-115
lines changed

2 files changed

+115
-115
lines changed

‎src/intrinsics/mod.rs

Lines changed: 0 additions & 115 deletions
Original file line numberDiff line numberDiff line change
@@ -234,121 +234,6 @@ fn bool_to_zero_or_max_uint<'tcx>(
234234
CValue::by_val(res, layout)
235235
}
236236

237-
macro simd_cmp {
238-
($fx:expr, $cc:ident|$cc_f:ident($x:ident, $y:ident) -> $ret:ident) => {
239-
let vector_ty = clif_vector_type($fx.tcx, $x.layout());
240-
241-
if let Some(vector_ty) = vector_ty {
242-
let x = $x.load_scalar($fx);
243-
let y = $y.load_scalar($fx);
244-
let val = if vector_ty.lane_type().is_float() {
245-
$fx.bcx.ins().fcmp(FloatCC::$cc_f, x, y)
246-
} else {
247-
$fx.bcx.ins().icmp(IntCC::$cc, x, y)
248-
};
249-
250-
// HACK This depends on the fact that icmp for vectors represents bools as 0 and !0, not 0 and 1.
251-
let val = $fx.bcx.ins().raw_bitcast(vector_ty, val);
252-
253-
$ret.write_cvalue($fx, CValue::by_val(val, $ret.layout()));
254-
} else {
255-
simd_pair_for_each_lane(
256-
$fx,
257-
$x,
258-
$y,
259-
$ret,
260-
|fx, lane_layout, res_lane_layout, x_lane, y_lane| {
261-
let res_lane = match lane_layout.ty.kind() {
262-
ty::Uint(_) | ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc, x_lane, y_lane),
263-
ty::Float(_) => fx.bcx.ins().fcmp(FloatCC::$cc_f, x_lane, y_lane),
264-
_ => unreachable!("{:?}", lane_layout.ty),
265-
};
266-
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
267-
},
268-
);
269-
}
270-
},
271-
($fx:expr, $cc_u:ident|$cc_s:ident|$cc_f:ident($x:ident, $y:ident) -> $ret:ident) => {
272-
// FIXME use vector icmp when possible
273-
simd_pair_for_each_lane(
274-
$fx,
275-
$x,
276-
$y,
277-
$ret,
278-
|fx, lane_layout, res_lane_layout, x_lane, y_lane| {
279-
let res_lane = match lane_layout.ty.kind() {
280-
ty::Uint(_) => fx.bcx.ins().icmp(IntCC::$cc_u, x_lane, y_lane),
281-
ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc_s, x_lane, y_lane),
282-
ty::Float(_) => fx.bcx.ins().fcmp(FloatCC::$cc_f, x_lane, y_lane),
283-
_ => unreachable!("{:?}", lane_layout.ty),
284-
};
285-
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
286-
},
287-
);
288-
},
289-
}
290-
291-
macro simd_int_binop {
292-
($fx:expr, $op:ident($x:ident, $y:ident) -> $ret:ident) => {
293-
simd_int_binop!($fx, $op|$op($x, $y) -> $ret);
294-
},
295-
($fx:expr, $op_u:ident|$op_s:ident($x:ident, $y:ident) -> $ret:ident) => {
296-
simd_pair_for_each_lane(
297-
$fx,
298-
$x,
299-
$y,
300-
$ret,
301-
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
302-
let res_lane = match lane_layout.ty.kind() {
303-
ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
304-
ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
305-
_ => unreachable!("{:?}", lane_layout.ty),
306-
};
307-
CValue::by_val(res_lane, ret_lane_layout)
308-
},
309-
);
310-
},
311-
}
312-
313-
macro simd_int_flt_binop {
314-
($fx:expr, $op:ident|$op_f:ident($x:ident, $y:ident) -> $ret:ident) => {
315-
simd_int_flt_binop!($fx, $op|$op|$op_f($x, $y) -> $ret);
316-
},
317-
($fx:expr, $op_u:ident|$op_s:ident|$op_f:ident($x:ident, $y:ident) -> $ret:ident) => {
318-
simd_pair_for_each_lane(
319-
$fx,
320-
$x,
321-
$y,
322-
$ret,
323-
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
324-
let res_lane = match lane_layout.ty.kind() {
325-
ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
326-
ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
327-
ty::Float(_) => fx.bcx.ins().$op_f(x_lane, y_lane),
328-
_ => unreachable!("{:?}", lane_layout.ty),
329-
};
330-
CValue::by_val(res_lane, ret_lane_layout)
331-
},
332-
);
333-
},
334-
}
335-
336-
macro simd_flt_binop($fx:expr, $op:ident($x:ident, $y:ident) -> $ret:ident) {
337-
simd_pair_for_each_lane(
338-
$fx,
339-
$x,
340-
$y,
341-
$ret,
342-
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
343-
let res_lane = match lane_layout.ty.kind() {
344-
ty::Float(_) => fx.bcx.ins().$op(x_lane, y_lane),
345-
_ => unreachable!("{:?}", lane_layout.ty),
346-
};
347-
CValue::by_val(res_lane, ret_lane_layout)
348-
},
349-
);
350-
}
351-
352237
pub(crate) fn codegen_intrinsic_call<'tcx>(
353238
fx: &mut FunctionCx<'_, '_, 'tcx>,
354239
instance: Instance<'tcx>,

‎src/intrinsics/simd.rs

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,121 @@ fn validate_simd_type(fx: &mut FunctionCx<'_, '_, '_>, intrinsic: Symbol, span:
1515
}
1616
}
1717

18+
macro simd_cmp {
19+
($fx:expr, $cc:ident|$cc_f:ident($x:ident, $y:ident) -> $ret:ident) => {
20+
let vector_ty = clif_vector_type($fx.tcx, $x.layout());
21+
22+
if let Some(vector_ty) = vector_ty {
23+
let x = $x.load_scalar($fx);
24+
let y = $y.load_scalar($fx);
25+
let val = if vector_ty.lane_type().is_float() {
26+
$fx.bcx.ins().fcmp(FloatCC::$cc_f, x, y)
27+
} else {
28+
$fx.bcx.ins().icmp(IntCC::$cc, x, y)
29+
};
30+
31+
// HACK This depends on the fact that icmp for vectors represents bools as 0 and !0, not 0 and 1.
32+
let val = $fx.bcx.ins().raw_bitcast(vector_ty, val);
33+
34+
$ret.write_cvalue($fx, CValue::by_val(val, $ret.layout()));
35+
} else {
36+
simd_pair_for_each_lane(
37+
$fx,
38+
$x,
39+
$y,
40+
$ret,
41+
|fx, lane_layout, res_lane_layout, x_lane, y_lane| {
42+
let res_lane = match lane_layout.ty.kind() {
43+
ty::Uint(_) | ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc, x_lane, y_lane),
44+
ty::Float(_) => fx.bcx.ins().fcmp(FloatCC::$cc_f, x_lane, y_lane),
45+
_ => unreachable!("{:?}", lane_layout.ty),
46+
};
47+
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
48+
},
49+
);
50+
}
51+
},
52+
($fx:expr, $cc_u:ident|$cc_s:ident|$cc_f:ident($x:ident, $y:ident) -> $ret:ident) => {
53+
// FIXME use vector icmp when possible
54+
simd_pair_for_each_lane(
55+
$fx,
56+
$x,
57+
$y,
58+
$ret,
59+
|fx, lane_layout, res_lane_layout, x_lane, y_lane| {
60+
let res_lane = match lane_layout.ty.kind() {
61+
ty::Uint(_) => fx.bcx.ins().icmp(IntCC::$cc_u, x_lane, y_lane),
62+
ty::Int(_) => fx.bcx.ins().icmp(IntCC::$cc_s, x_lane, y_lane),
63+
ty::Float(_) => fx.bcx.ins().fcmp(FloatCC::$cc_f, x_lane, y_lane),
64+
_ => unreachable!("{:?}", lane_layout.ty),
65+
};
66+
bool_to_zero_or_max_uint(fx, res_lane_layout, res_lane)
67+
},
68+
);
69+
},
70+
}
71+
72+
macro simd_int_binop {
73+
($fx:expr, $op:ident($x:ident, $y:ident) -> $ret:ident) => {
74+
simd_int_binop!($fx, $op|$op($x, $y) -> $ret);
75+
},
76+
($fx:expr, $op_u:ident|$op_s:ident($x:ident, $y:ident) -> $ret:ident) => {
77+
simd_pair_for_each_lane(
78+
$fx,
79+
$x,
80+
$y,
81+
$ret,
82+
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
83+
let res_lane = match lane_layout.ty.kind() {
84+
ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
85+
ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
86+
_ => unreachable!("{:?}", lane_layout.ty),
87+
};
88+
CValue::by_val(res_lane, ret_lane_layout)
89+
},
90+
);
91+
},
92+
}
93+
94+
macro simd_int_flt_binop {
95+
($fx:expr, $op:ident|$op_f:ident($x:ident, $y:ident) -> $ret:ident) => {
96+
simd_int_flt_binop!($fx, $op|$op|$op_f($x, $y) -> $ret);
97+
},
98+
($fx:expr, $op_u:ident|$op_s:ident|$op_f:ident($x:ident, $y:ident) -> $ret:ident) => {
99+
simd_pair_for_each_lane(
100+
$fx,
101+
$x,
102+
$y,
103+
$ret,
104+
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
105+
let res_lane = match lane_layout.ty.kind() {
106+
ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
107+
ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
108+
ty::Float(_) => fx.bcx.ins().$op_f(x_lane, y_lane),
109+
_ => unreachable!("{:?}", lane_layout.ty),
110+
};
111+
CValue::by_val(res_lane, ret_lane_layout)
112+
},
113+
);
114+
},
115+
}
116+
117+
macro simd_flt_binop($fx:expr, $op:ident($x:ident, $y:ident) -> $ret:ident) {
118+
simd_pair_for_each_lane(
119+
$fx,
120+
$x,
121+
$y,
122+
$ret,
123+
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
124+
let res_lane = match lane_layout.ty.kind() {
125+
ty::Float(_) => fx.bcx.ins().$op(x_lane, y_lane),
126+
_ => unreachable!("{:?}", lane_layout.ty),
127+
};
128+
CValue::by_val(res_lane, ret_lane_layout)
129+
},
130+
);
131+
}
132+
18133
pub(super) fn codegen_simd_intrinsic_call<'tcx>(
19134
fx: &mut FunctionCx<'_, '_, 'tcx>,
20135
intrinsic: Symbol,

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