Skip to content

Commit 9295b08

Browse files
bjorn3bjorn3
committed
Turn validate_simd_type into a function
This effectively outlines it, significantly reducing the size of the codegen_simd_intrinsic_call llvm ir from 10419 lines to 6378 lines.
1 parent 9e6d8c1 commit 9295b08

File tree

2 files changed

+44
-44
lines changed

2 files changed

+44
-44
lines changed

‎src/intrinsics/mod.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -91,11 +91,11 @@ macro validate_atomic_type($fx:ident, $intrinsic:ident, $span:ident, $ty:expr) {
9191
}
9292
}
9393

94-
macro validate_simd_type($fx:ident, $intrinsic:ident, $span:ident, $ty:expr) {
95-
if !$ty.is_simd() {
96-
$fx.tcx.sess.span_err($span, &format!("invalid monomorphization of `{}` intrinsic: expected SIMD input type, found non-SIMD `{}`", $intrinsic, $ty));
94+
fn validate_simd_type(fx: &mut FunctionCx<'_, '_, '_>, intrinsic: Symbol, span: Span, ty: Ty<'_>) {
95+
if !ty.is_simd() {
96+
fx.tcx.sess.span_err(span, &format!("invalid monomorphization of `{}` intrinsic: expected SIMD input type, found non-SIMD `{}`", intrinsic, ty));
9797
// Prevent verifier error
98-
crate::trap::trap_unreachable($fx, "compilation should not have succeeded");
98+
crate::trap::trap_unreachable(fx, "compilation should not have succeeded");
9999
return;
100100
}
101101
}

‎src/intrinsics/simd.rs

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
2121
};
2222

2323
simd_cast, (c a) {
24-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
24+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
2525
simd_for_each_lane(fx, a, ret, |fx, lane_layout, ret_lane_layout, lane| {
2626
let ret_lane_ty = fx.clif_type(ret_lane_layout.ty).unwrap();
2727

@@ -34,27 +34,27 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
3434
};
3535

3636
simd_eq, (c x, c y) {
37-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
37+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
3838
simd_cmp!(fx, Equal|Equal(x, y) -> ret);
3939
};
4040
simd_ne, (c x, c y) {
41-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
41+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
4242
simd_cmp!(fx, NotEqual|NotEqual(x, y) -> ret);
4343
};
4444
simd_lt, (c x, c y) {
45-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
45+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
4646
simd_cmp!(fx, UnsignedLessThan|SignedLessThan|LessThan(x, y) -> ret);
4747
};
4848
simd_le, (c x, c y) {
49-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
49+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
5050
simd_cmp!(fx, UnsignedLessThanOrEqual|SignedLessThanOrEqual|LessThanOrEqual(x, y) -> ret);
5151
};
5252
simd_gt, (c x, c y) {
53-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
53+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
5454
simd_cmp!(fx, UnsignedGreaterThan|SignedGreaterThan|GreaterThan(x, y) -> ret);
5555
};
5656
simd_ge, (c x, c y) {
57-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
57+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
5858
simd_cmp!(
5959
fx,
6060
UnsignedGreaterThanOrEqual|SignedGreaterThanOrEqual|GreaterThanOrEqual
@@ -64,7 +64,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
6464

6565
// simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U
6666
_ if intrinsic.as_str().starts_with("simd_shuffle"), (c x, c y, o idx) {
67-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
67+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
6868

6969
// If this intrinsic is the older "simd_shuffleN" form, simply parse the integer.
7070
// If there is no suffix, use the index array length.
@@ -166,7 +166,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
166166
};
167167

168168
simd_extract, (c v, o idx) {
169-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
169+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
170170
let idx_const = if let Some(idx_const) = crate::constant::mir_operand_get_const_val(fx, idx) {
171171
idx_const
172172
} else {
@@ -194,7 +194,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
194194
};
195195

196196
simd_neg, (c a) {
197-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
197+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
198198
simd_for_each_lane(fx, a, ret, |fx, lane_layout, ret_lane_layout, lane| {
199199
let ret_lane = match lane_layout.ty.kind() {
200200
ty::Int(_) => fx.bcx.ins().ineg(lane),
@@ -206,39 +206,39 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
206206
};
207207

208208
simd_fabs, (c a) {
209-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
209+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
210210
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
211211
let ret_lane = fx.bcx.ins().fabs(lane);
212212
CValue::by_val(ret_lane, ret_lane_layout)
213213
});
214214
};
215215

216216
simd_fsqrt, (c a) {
217-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
217+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
218218
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
219219
let ret_lane = fx.bcx.ins().sqrt(lane);
220220
CValue::by_val(ret_lane, ret_lane_layout)
221221
});
222222
};
223223

224224
simd_add, (c x, c y) {
225-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
225+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
226226
simd_int_flt_binop!(fx, iadd|fadd(x, y) -> ret);
227227
};
228228
simd_sub, (c x, c y) {
229-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
229+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
230230
simd_int_flt_binop!(fx, isub|fsub(x, y) -> ret);
231231
};
232232
simd_mul, (c x, c y) {
233-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
233+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
234234
simd_int_flt_binop!(fx, imul|fmul(x, y) -> ret);
235235
};
236236
simd_div, (c x, c y) {
237-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
237+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
238238
simd_int_flt_binop!(fx, udiv|sdiv|fdiv(x, y) -> ret);
239239
};
240240
simd_rem, (c x, c y) {
241-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
241+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
242242
simd_pair_for_each_lane(fx, x, y, ret, |fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
243243
let res_lane = match lane_layout.ty.kind() {
244244
ty::Uint(_) => fx.bcx.ins().urem(x_lane, y_lane),
@@ -261,28 +261,28 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
261261
});
262262
};
263263
simd_shl, (c x, c y) {
264-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
264+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
265265
simd_int_binop!(fx, ishl(x, y) -> ret);
266266
};
267267
simd_shr, (c x, c y) {
268-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
268+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
269269
simd_int_binop!(fx, ushr|sshr(x, y) -> ret);
270270
};
271271
simd_and, (c x, c y) {
272-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
272+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
273273
simd_int_binop!(fx, band(x, y) -> ret);
274274
};
275275
simd_or, (c x, c y) {
276-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
276+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
277277
simd_int_binop!(fx, bor(x, y) -> ret);
278278
};
279279
simd_xor, (c x, c y) {
280-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
280+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
281281
simd_int_binop!(fx, bxor(x, y) -> ret);
282282
};
283283

284284
simd_fma, (c a, c b, c c) {
285-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
285+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
286286
assert_eq!(a.layout(), b.layout());
287287
assert_eq!(a.layout(), c.layout());
288288
let layout = a.layout();
@@ -305,16 +305,16 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
305305
};
306306

307307
simd_fmin, (c x, c y) {
308-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
308+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
309309
simd_flt_binop!(fx, fmin(x, y) -> ret);
310310
};
311311
simd_fmax, (c x, c y) {
312-
validate_simd_type!(fx, intrinsic, span, x.layout().ty);
312+
validate_simd_type(fx, intrinsic, span, x.layout().ty);
313313
simd_flt_binop!(fx, fmax(x, y) -> ret);
314314
};
315315

316316
simd_round, (c a) {
317-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
317+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
318318
simd_for_each_lane(fx, a, ret, |fx, lane_layout, ret_lane_layout, lane| {
319319
let res_lane = match lane_layout.ty.kind() {
320320
ty::Float(FloatTy::F32) => fx.lib_call(
@@ -335,29 +335,29 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
335335
});
336336
};
337337
simd_ceil, (c a) {
338-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
338+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
339339
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
340340
let ret_lane = fx.bcx.ins().ceil(lane);
341341
CValue::by_val(ret_lane, ret_lane_layout)
342342
});
343343
};
344344
simd_floor, (c a) {
345-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
345+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
346346
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
347347
let ret_lane = fx.bcx.ins().floor(lane);
348348
CValue::by_val(ret_lane, ret_lane_layout)
349349
});
350350
};
351351
simd_trunc, (c a) {
352-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
352+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
353353
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
354354
let ret_lane = fx.bcx.ins().trunc(lane);
355355
CValue::by_val(ret_lane, ret_lane_layout)
356356
});
357357
};
358358

359359
simd_reduce_add_ordered | simd_reduce_add_unordered, (c v, v acc) {
360-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
360+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
361361
simd_reduce(fx, v, Some(acc), ret, |fx, lane_layout, a, b| {
362362
if lane_layout.ty.is_floating_point() {
363363
fx.bcx.ins().fadd(a, b)
@@ -368,7 +368,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
368368
};
369369

370370
simd_reduce_mul_ordered | simd_reduce_mul_unordered, (c v, v acc) {
371-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
371+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
372372
simd_reduce(fx, v, Some(acc), ret, |fx, lane_layout, a, b| {
373373
if lane_layout.ty.is_floating_point() {
374374
fx.bcx.ins().fmul(a, b)
@@ -379,32 +379,32 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
379379
};
380380

381381
simd_reduce_all, (c v) {
382-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
382+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
383383
simd_reduce_bool(fx, v, ret, |fx, a, b| fx.bcx.ins().band(a, b));
384384
};
385385

386386
simd_reduce_any, (c v) {
387-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
387+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
388388
simd_reduce_bool(fx, v, ret, |fx, a, b| fx.bcx.ins().bor(a, b));
389389
};
390390

391391
simd_reduce_and, (c v) {
392-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
392+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
393393
simd_reduce(fx, v, None, ret, |fx, _layout, a, b| fx.bcx.ins().band(a, b));
394394
};
395395

396396
simd_reduce_or, (c v) {
397-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
397+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
398398
simd_reduce(fx, v, None, ret, |fx, _layout, a, b| fx.bcx.ins().bor(a, b));
399399
};
400400

401401
simd_reduce_xor, (c v) {
402-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
402+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
403403
simd_reduce(fx, v, None, ret, |fx, _layout, a, b| fx.bcx.ins().bxor(a, b));
404404
};
405405

406406
simd_reduce_min, (c v) {
407-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
407+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
408408
simd_reduce(fx, v, None, ret, |fx, layout, a, b| {
409409
let lt = match layout.ty.kind() {
410410
ty::Int(_) => fx.bcx.ins().icmp(IntCC::SignedLessThan, a, b),
@@ -417,7 +417,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
417417
};
418418

419419
simd_reduce_max, (c v) {
420-
validate_simd_type!(fx, intrinsic, span, v.layout().ty);
420+
validate_simd_type(fx, intrinsic, span, v.layout().ty);
421421
simd_reduce(fx, v, None, ret, |fx, layout, a, b| {
422422
let gt = match layout.ty.kind() {
423423
ty::Int(_) => fx.bcx.ins().icmp(IntCC::SignedGreaterThan, a, b),
@@ -430,8 +430,8 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
430430
};
431431

432432
simd_select, (c m, c a, c b) {
433-
validate_simd_type!(fx, intrinsic, span, m.layout().ty);
434-
validate_simd_type!(fx, intrinsic, span, a.layout().ty);
433+
validate_simd_type(fx, intrinsic, span, m.layout().ty);
434+
validate_simd_type(fx, intrinsic, span, a.layout().ty);
435435
assert_eq!(a.layout(), b.layout());
436436

437437
let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx);

0 commit comments

Comments
 (0)