Skip to content

Commit a65bf7a

Browse files
committed
Add amdgpu target
Add target and compile the amdgpu llvm backend.
1 parent e491cae commit a65bf7a

File tree

14 files changed

+180
-10
lines changed

14 files changed

+180
-10
lines changed

compiler/rustc_target/src/spec/mod.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1905,6 +1905,8 @@ supported_targets! {
19051905

19061906
("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
19071907

1908+
("amdgcn-amd-amdhsa", amdgcn_amd_amdhsa),
1909+
19081910
("xtensa-esp32-none-elf", xtensa_esp32_none_elf),
19091911
("xtensa-esp32-espidf", xtensa_esp32_espidf),
19101912
("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf),
Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, Target, TargetOptions};
2+
3+
pub(crate) fn target() -> Target {
4+
Target {
5+
arch: "amdgpu".into(),
6+
data_layout: "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(),
7+
llvm_target: "amdgcn-amd-amdhsa".into(),
8+
metadata: crate::spec::TargetMetadata {
9+
description: Some("AMD GPU".into()),
10+
tier: Some(3),
11+
host_tools: Some(false),
12+
std: Some(false),
13+
},
14+
pointer_width: 64,
15+
16+
options: TargetOptions {
17+
os: "amdhsa".into(),
18+
vendor: "amd".into(),
19+
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
20+
linker: Some("rust-lld".into()),
21+
22+
max_atomic_width: Some(64),
23+
24+
// Unwinding on GPUs is not useful.
25+
panic_strategy: PanicStrategy::Abort,
26+
27+
// amdgpu backend does not support libcalls.
28+
no_builtins: true,
29+
simd_types_indirect: false,
30+
31+
// Allow `cdylib` crate type.
32+
dynamic_linking: true,
33+
only_cdylib: true,
34+
executables: false,
35+
dll_prefix: "".into(),
36+
dll_suffix: ".elf".into(),
37+
38+
// The LLVM backend does not support stack canaries for this target
39+
supports_stack_protector: false,
40+
41+
// Force LTO, object linking does not yet work with amdgpu.
42+
requires_lto: true,
43+
44+
..Default::default()
45+
},
46+
}
47+
}

config.example.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@
108108
# the resulting rustc being unable to compile for the disabled architectures.
109109
#
110110
# To add support for new targets, see https://rustc-dev-guide.rust-lang.org/building/new-target.html.
111-
#targets = "AArch64;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
111+
#targets = "AArch64;AMDGPU;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
112112

113113
# LLVM experimental targets to build support for. These targets are specified in
114114
# the same format as above, but since these targets are experimental, they are
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
Change this file to make users of the `download-ci-llvm` configuration download
22
a new version of LLVM from CI, even if the LLVM submodule hasn’t changed.
33

4-
Last change is for: https://github.com/rust-lang/rust/pull/129788
4+
Last change is for: https://github.com/rust-lang/rust/pull/134740

src/bootstrap/src/core/build_steps/llvm.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,7 @@ impl Step for Llvm {
331331
let llvm_targets = match &builder.config.llvm_targets {
332332
Some(s) => s,
333333
None => {
334-
"AArch64;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;\
334+
"AArch64;AMDGPU;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;\
335335
Sparc;SystemZ;WebAssembly;X86"
336336
}
337337
};

src/doc/rustc/src/SUMMARY.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
- [\*-apple-watchos](platform-support/apple-watchos.md)
3030
- [\*-apple-visionos](platform-support/apple-visionos.md)
3131
- [aarch64-nintendo-switch-freestanding](platform-support/aarch64-nintendo-switch-freestanding.md)
32+
- [amdgcn-amd-amdhsa](platform-support/amdgcn-amd-amdhsa.md)
3233
- [armeb-unknown-linux-gnueabi](platform-support/armeb-unknown-linux-gnueabi.md)
3334
- [arm-none-eabi](platform-support/arm-none-eabi.md)
3435
- [armv4t-none-eabi](platform-support/armv4t-none-eabi.md)

src/doc/rustc/src/platform-support.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -269,6 +269,7 @@ target | std | host | notes
269269
`aarch64_be-unknown-linux-gnu` | ✓ | ✓ | ARM64 Linux (big-endian)
270270
`aarch64_be-unknown-linux-gnu_ilp32` | ✓ | ✓ | ARM64 Linux (big-endian, ILP32 ABI)
271271
[`aarch64_be-unknown-netbsd`](platform-support/netbsd.md) | ✓ | ✓ | ARM64 NetBSD (big-endian)
272+
[`amdgcn-amd-amdhsa`](platform-support/amdgcn-amd-amdhsa.md) | * | | `-Ctarget-cpu=gfx...` to specify [the AMD GPU] to compile for
272273
[`arm64_32-apple-watchos`](platform-support/apple-watchos.md) | ✓ | | Arm Apple WatchOS 64-bit with 32-bit pointers
273274
[`arm64e-apple-darwin`](platform-support/arm64e-apple-darwin.md) | ✓ | ✓ | ARM64e Apple Darwin
274275
[`arm64e-apple-ios`](platform-support/arm64e-apple-ios.md) | ✓ | | ARM64e Apple iOS
@@ -423,3 +424,4 @@ target | std | host | notes
423424
[`xtensa-esp32s3-none-elf`](platform-support/xtensa.md) | * | | Xtensa ESP32-S3
424425

425426
[runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets
427+
[the AMD GPU]: https://llvm.org/docs/AMDGPUUsage.html#processors
Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,96 @@
1+
# `amdgcn-amd-amdhsa`
2+
3+
**Tier: 3**
4+
5+
AMD GPU target for compute/HSA (Heterogeneous System Architecture).
6+
7+
## Target maintainers
8+
9+
- [@Flakebi](https://github.com/Flakebi)
10+
11+
## Requirements
12+
13+
AMD GPUs can be targeted via cross-compilation.
14+
The default binary format is ELF.
15+
Binaries can be loaded by the HSA runtime implemented in [ROCR-Runtime].
16+
17+
Binaries must be built with no-std.
18+
They can use `core` and `alloc` (`alloc` only if an allocator is supplied).
19+
At least one function needs to use the `"amdgpu-kernel"` calling convention.
20+
These functions can be used as kernel entrypoints in HSA.
21+
22+
## Building the target
23+
24+
The target is included in rustc.
25+
26+
## Building Rust programs
27+
28+
The amdgpu target supports many hardware generations, which need different binaries.
29+
The generations are all exposed as different target-cpus in the backend.
30+
As there are many, Rust does not ship pre-compiled libraries for this target.
31+
Therefore, you have to build your own copy of `core` by using `cargo -Zbuild-std=core` or similar.
32+
33+
To build a binary that can be loaded with HSA, create a no-std library:
34+
```rust,ignore (platform-specific)
35+
// src/lib.rs
36+
#![feature(abi_amdgpu_kernel)]
37+
#![no_std]
38+
39+
#[panic_handler]
40+
fn panic(_: &core::panic::PanicInfo) -> ! {
41+
loop {}
42+
}
43+
44+
#[no_mangle]
45+
pub extern "amdgpu-kernel" fn kernel(/* Arguments */) {
46+
// Code
47+
}
48+
```
49+
50+
Build the library as `cdylib`:
51+
```toml
52+
# Cargo.toml
53+
[lib]
54+
crate-type = ["cdylib"]
55+
56+
[profile.dev]
57+
lto = true # LTO must be explicitly enabled for now
58+
[profile.release]
59+
lto = true
60+
```
61+
62+
The target-cpu must be from the list [supported by LLVM] (or printed with `rustc --target amdgcn-amd-amdhsa --print target-cpus`).
63+
The GPU version on the current system can be found e.g. with [`rocminfo`].
64+
65+
Example `.cargo/config.toml` file to set the target and GPU generation:
66+
```toml
67+
# .cargo/config.toml
68+
[build]
69+
target = "amdgcn-amd-amdhsa"
70+
rustflags = ["-Ctarget-cpu=gfx1100"]
71+
72+
[unstable]
73+
build-std = ["core"] # Optional: "alloc"
74+
```
75+
76+
<!-- Mention an allocator once a suitable one exists for amdgpu -->
77+
78+
<!-- Mention HSA bindings once they work
79+
80+
## Testing
81+
82+
Does the target support running binaries, or do binaries have varying
83+
expectations that prevent having a standard way to run them? If users can run
84+
binaries, can they do so in some common emulator, or do they need native
85+
hardware? Does the target support running the Rust testsuite?
86+
87+
-->
88+
89+
## Additional information
90+
91+
More information can be found on the [LLVM page for amdgpu]
92+
93+
[ROCR-Runtime]: https://github.com/ROCm/ROCR-Runtime
94+
[supported by LLVM]: https://llvm.org/docs/AMDGPUUsage.html#processors
95+
[LLVM page for amdgpu]: https://llvm.org/docs/AMDGPUUsage.html
96+
[`rocminfo`]: https://github.com/ROCm/rocminfo

src/tools/build-manifest/src/main.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ static TARGETS: &[&str] = &[
6767
"aarch64-unknown-none-softfloat",
6868
"aarch64-unknown-redox",
6969
"aarch64-unknown-uefi",
70+
"amdgcn-amd-amdhsa",
7071
"arm64e-apple-darwin",
7172
"arm64e-apple-ios",
7273
"arm64e-apple-tvos",
Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
//@ assembly-output: emit-asm
2+
// ignore-tidy-linelength
3+
//@ revisions: amdgcn_amd_amdhsa
4+
//@ [amdgcn_amd_amdhsa] compile-flags: --target amdgcn-amd-amdhsa
5+
//@ [amdgcn_amd_amdhsa] needs-llvm-components: amdgpu
6+
7+
// Sanity-check that each target can produce assembly code.
8+
9+
#![feature(no_core, lang_items)]
10+
#![no_std]
11+
#![no_core]
12+
#![crate_type = "lib"]
13+
14+
#[lang = "sized"]
15+
trait Sized {}
16+
17+
pub fn test() -> u8 {
18+
42
19+
}
20+
21+
// CHECK: .version

0 commit comments

Comments
 (0)