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bjorn3bjorn3
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Return Value instead of CValue from the simd_for_each_lane closure
1 parent 57d25ef commit b60eced

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3 files changed

+42
-56
lines changed

3 files changed

+42
-56
lines changed

‎src/intrinsics/llvm.rs

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -83,22 +83,20 @@ pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
8383
};
8484
"llvm.x86.sse2.psrli.d", (c a, o imm8) {
8585
let imm8 = crate::constant::mir_operand_get_const_val(fx, imm8).expect("llvm.x86.sse2.psrli.d imm8 not const");
86-
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, res_lane_layout, lane| {
87-
let res_lane = match imm8.try_to_bits(Size::from_bytes(4)).unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8)) {
86+
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, _res_lane_layout, lane| {
87+
match imm8.try_to_bits(Size::from_bytes(4)).unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8)) {
8888
imm8 if imm8 < 32 => fx.bcx.ins().ushr_imm(lane, i64::from(imm8 as u8)),
8989
_ => fx.bcx.ins().iconst(types::I32, 0),
90-
};
91-
CValue::by_val(res_lane, res_lane_layout)
90+
}
9291
});
9392
};
9493
"llvm.x86.sse2.pslli.d", (c a, o imm8) {
9594
let imm8 = crate::constant::mir_operand_get_const_val(fx, imm8).expect("llvm.x86.sse2.psrli.d imm8 not const");
96-
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, res_lane_layout, lane| {
97-
let res_lane = match imm8.try_to_bits(Size::from_bytes(4)).unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8)) {
95+
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, _res_lane_layout, lane| {
96+
match imm8.try_to_bits(Size::from_bytes(4)).unwrap_or_else(|| panic!("imm8 not scalar: {:?}", imm8)) {
9897
imm8 if imm8 < 32 => fx.bcx.ins().ishl_imm(lane, i64::from(imm8 as u8)),
9998
_ => fx.bcx.ins().iconst(types::I32, 0),
100-
};
101-
CValue::by_val(res_lane, res_lane_layout)
99+
}
102100
});
103101
};
104102
"llvm.x86.sse2.storeu.dq", (v mem_addr, c a) {

‎src/intrinsics/mod.rs

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ fn simd_for_each_lane<'tcx>(
113113
TyAndLayout<'tcx>,
114114
TyAndLayout<'tcx>,
115115
Value,
116-
) -> CValue<'tcx>,
116+
) -> Value,
117117
) {
118118
let layout = val.layout();
119119

@@ -127,6 +127,7 @@ fn simd_for_each_lane<'tcx>(
127127
let lane = val.value_lane(fx, lane_idx).load_scalar(fx);
128128

129129
let res_lane = f(fx, lane_layout, ret_lane_layout, lane);
130+
let res_lane = CValue::by_val(res_lane, ret_lane_layout);
130131

131132
ret.place_lane(fx, lane_idx).write_cvalue(fx, res_lane);
132133
}
@@ -143,7 +144,7 @@ fn simd_pair_for_each_lane<'tcx>(
143144
TyAndLayout<'tcx>,
144145
Value,
145146
Value,
146-
) -> CValue<'tcx>,
147+
) -> Value,
147148
) {
148149
assert_eq!(x.layout(), y.layout());
149150
let layout = x.layout();
@@ -159,6 +160,7 @@ fn simd_pair_for_each_lane<'tcx>(
159160
let y_lane = y.value_lane(fx, lane_idx).load_scalar(fx);
160161

161162
let res_lane = f(fx, lane_layout, ret_lane_layout, x_lane, y_lane);
163+
let res_lane = CValue::by_val(res_lane, ret_lane_layout);
162164

163165
ret.place_lane(fx, lane_idx).write_cvalue(fx, res_lane);
164166
}
@@ -215,7 +217,7 @@ fn bool_to_zero_or_max_uint<'tcx>(
215217
fx: &mut FunctionCx<'_, '_, 'tcx>,
216218
layout: TyAndLayout<'tcx>,
217219
val: Value,
218-
) -> CValue<'tcx> {
220+
) -> Value {
219221
let ty = fx.clif_type(layout.ty).unwrap();
220222

221223
let int_ty = match ty {
@@ -231,7 +233,7 @@ fn bool_to_zero_or_max_uint<'tcx>(
231233
res = fx.bcx.ins().bitcast(ty, res);
232234
}
233235

234-
CValue::by_val(res, layout)
236+
res
235237
}
236238

237239
pub(crate) fn codegen_intrinsic_call<'tcx>(

‎src/intrinsics/simd.rs

Lines changed: 30 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,7 @@ macro simd_cmp($fx:expr, $cc_u:ident|$cc_s:ident|$cc_f:ident($x:ident, $y:ident)
3333
let ty = fx.clif_type(res_lane_layout.ty).unwrap();
3434

3535
let res_lane = fx.bcx.ins().bint(ty, res_lane);
36-
let res_lane = fx.bcx.ins().ineg(res_lane);
37-
38-
CValue::by_val(res_lane, res_lane_layout)
36+
fx.bcx.ins().ineg(res_lane)
3937
},
4038
);
4139
}
@@ -47,13 +45,12 @@ macro simd_int_binop($fx:expr, $op_u:ident|$op_s:ident($x:ident, $y:ident) -> $r
4745
$x,
4846
$y,
4947
$ret,
50-
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
51-
let res_lane = match lane_layout.ty.kind() {
48+
|fx, lane_layout, _ret_lane_layout, x_lane, y_lane| {
49+
match lane_layout.ty.kind() {
5250
ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
5351
ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
5452
_ => unreachable!("{:?}", lane_layout.ty),
55-
};
56-
CValue::by_val(res_lane, ret_lane_layout)
53+
}
5754
},
5855
);
5956
}
@@ -65,14 +62,13 @@ macro simd_int_flt_binop($fx:expr, $op_u:ident|$op_s:ident|$op_f:ident($x:ident,
6562
$x,
6663
$y,
6764
$ret,
68-
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
69-
let res_lane = match lane_layout.ty.kind() {
65+
|fx, lane_layout, _ret_lane_layout, x_lane, y_lane| {
66+
match lane_layout.ty.kind() {
7067
ty::Uint(_) => fx.bcx.ins().$op_u(x_lane, y_lane),
7168
ty::Int(_) => fx.bcx.ins().$op_s(x_lane, y_lane),
7269
ty::Float(_) => fx.bcx.ins().$op_f(x_lane, y_lane),
7370
_ => unreachable!("{:?}", lane_layout.ty),
74-
};
75-
CValue::by_val(res_lane, ret_lane_layout)
71+
}
7672
},
7773
);
7874
}
@@ -84,12 +80,11 @@ macro simd_flt_binop($fx:expr, $op:ident($x:ident, $y:ident) -> $ret:ident) {
8480
$x,
8581
$y,
8682
$ret,
87-
|fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
88-
let res_lane = match lane_layout.ty.kind() {
83+
|fx, lane_layout, _ret_lane_layout, x_lane, y_lane| {
84+
match lane_layout.ty.kind() {
8985
ty::Float(_) => fx.bcx.ins().$op(x_lane, y_lane),
9086
_ => unreachable!("{:?}", lane_layout.ty),
91-
};
92-
CValue::by_val(res_lane, ret_lane_layout)
87+
}
9388
},
9489
);
9590
}
@@ -116,8 +111,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
116111
let from_signed = type_sign(lane_layout.ty);
117112
let to_signed = type_sign(ret_lane_layout.ty);
118113

119-
let ret_lane = clif_int_or_float_cast(fx, lane, from_signed, ret_lane_ty, to_signed);
120-
CValue::by_val(ret_lane, ret_lane_layout)
114+
clif_int_or_float_cast(fx, lane, from_signed, ret_lane_ty, to_signed)
121115
});
122116
};
123117

@@ -283,29 +277,26 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
283277

284278
simd_neg, (c a) {
285279
validate_simd_type(fx, intrinsic, span, a.layout().ty);
286-
simd_for_each_lane(fx, a, ret, |fx, lane_layout, ret_lane_layout, lane| {
287-
let ret_lane = match lane_layout.ty.kind() {
280+
simd_for_each_lane(fx, a, ret, |fx, lane_layout, _ret_lane_layout, lane| {
281+
match lane_layout.ty.kind() {
288282
ty::Int(_) => fx.bcx.ins().ineg(lane),
289283
ty::Float(_) => fx.bcx.ins().fneg(lane),
290284
_ => unreachable!(),
291-
};
292-
CValue::by_val(ret_lane, ret_lane_layout)
285+
}
293286
});
294287
};
295288

296289
simd_fabs, (c a) {
297290
validate_simd_type(fx, intrinsic, span, a.layout().ty);
298-
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
299-
let ret_lane = fx.bcx.ins().fabs(lane);
300-
CValue::by_val(ret_lane, ret_lane_layout)
291+
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, _ret_lane_layout, lane| {
292+
fx.bcx.ins().fabs(lane)
301293
});
302294
};
303295

304296
simd_fsqrt, (c a) {
305297
validate_simd_type(fx, intrinsic, span, a.layout().ty);
306-
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
307-
let ret_lane = fx.bcx.ins().sqrt(lane);
308-
CValue::by_val(ret_lane, ret_lane_layout)
298+
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, _ret_lane_layout, lane| {
299+
fx.bcx.ins().sqrt(lane)
309300
});
310301
};
311302

@@ -327,8 +318,8 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
327318
};
328319
simd_rem, (c x, c y) {
329320
validate_simd_type(fx, intrinsic, span, x.layout().ty);
330-
simd_pair_for_each_lane(fx, x, y, ret, |fx, lane_layout, ret_lane_layout, x_lane, y_lane| {
331-
let res_lane = match lane_layout.ty.kind() {
321+
simd_pair_for_each_lane(fx, x, y, ret, |fx, lane_layout, _ret_lane_layout, x_lane, y_lane| {
322+
match lane_layout.ty.kind() {
332323
ty::Uint(_) => fx.bcx.ins().urem(x_lane, y_lane),
333324
ty::Int(_) => fx.bcx.ins().srem(x_lane, y_lane),
334325
ty::Float(FloatTy::F32) => fx.lib_call(
@@ -344,8 +335,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
344335
&[x_lane, y_lane],
345336
)[0],
346337
_ => unreachable!("{:?}", lane_layout.ty),
347-
};
348-
CValue::by_val(res_lane, ret_lane_layout)
338+
}
349339
});
350340
};
351341
simd_shl, (c x, c y) {
@@ -403,8 +393,8 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
403393

404394
simd_round, (c a) {
405395
validate_simd_type(fx, intrinsic, span, a.layout().ty);
406-
simd_for_each_lane(fx, a, ret, |fx, lane_layout, ret_lane_layout, lane| {
407-
let res_lane = match lane_layout.ty.kind() {
396+
simd_for_each_lane(fx, a, ret, |fx, lane_layout, _ret_lane_layout, lane| {
397+
match lane_layout.ty.kind() {
408398
ty::Float(FloatTy::F32) => fx.lib_call(
409399
"roundf",
410400
vec![AbiParam::new(types::F32)],
@@ -418,29 +408,25 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
418408
&[lane],
419409
)[0],
420410
_ => unreachable!("{:?}", lane_layout.ty),
421-
};
422-
CValue::by_val(res_lane, ret_lane_layout)
411+
}
423412
});
424413
};
425414
simd_ceil, (c a) {
426415
validate_simd_type(fx, intrinsic, span, a.layout().ty);
427-
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
428-
let ret_lane = fx.bcx.ins().ceil(lane);
429-
CValue::by_val(ret_lane, ret_lane_layout)
416+
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, _ret_lane_layout, lane| {
417+
fx.bcx.ins().ceil(lane)
430418
});
431419
};
432420
simd_floor, (c a) {
433421
validate_simd_type(fx, intrinsic, span, a.layout().ty);
434-
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
435-
let ret_lane = fx.bcx.ins().floor(lane);
436-
CValue::by_val(ret_lane, ret_lane_layout)
422+
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, _ret_lane_layout, lane| {
423+
fx.bcx.ins().floor(lane)
437424
});
438425
};
439426
simd_trunc, (c a) {
440427
validate_simd_type(fx, intrinsic, span, a.layout().ty);
441-
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, ret_lane_layout, lane| {
442-
let ret_lane = fx.bcx.ins().trunc(lane);
443-
CValue::by_val(ret_lane, ret_lane_layout)
428+
simd_for_each_lane(fx, a, ret, |fx, _lane_layout, _ret_lane_layout, lane| {
429+
fx.bcx.ins().trunc(lane)
444430
});
445431
};
446432

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