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RISC-V: Add floating point state registers to inline assembly's clobber list
Against the reference, floating point state registers are not clobbered by default settings of RISC-V inline assembly. Of which, `fflags` is read/written by other LLVM instructions so that clobbering must be handled to avoid possible FP-related issues (and directly referenced by the reference as clobbered). `frm` is added for consistency with `vxrm`.
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compiler/rustc_codegen_llvm/src/asm.rs

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@@ -240,6 +240,8 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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constraints.extend_from_slice(&[
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"~{fflags}".to_string(),
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"~{frm}".to_string(),
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"~{vtype}".to_string(),
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"~{vl}".to_string(),
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"~{vxsat}".to_string(),

tests/codegen-llvm/asm/riscv-clobbers.rs

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@@ -17,7 +17,7 @@ extern crate minicore;
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use minicore::*;
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// CHECK-LABEL: @flags_clobber
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// CHECK: call void asm sideeffect "", "~{vtype},~{vl},~{vxsat},~{vxrm}"()
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// CHECK: call void asm sideeffect "", "~{fflags},~{frm},~{vtype},~{vl},~{vxsat},~{vxrm}"()
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#[no_mangle]
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pub unsafe fn flags_clobber() {
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asm!("", options(nostack, nomem));

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