From 6c463ccf058f6be456c5ae7f8a2af6ed55e5243b Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Tue, 7 Oct 2025 11:09:11 +0000 Subject: [PATCH] rustc_target: RISC-V: Add two supervisor extensions for intrinsics This commit adds two ratified **privileged** RISC-V extensions corresponding to 35 existing intrinsics in `core::arch::riscv{32,64}`. Because they semantically require the H and/or Svinval privileged extensions, we'd better to have those new target features to use them as a part of the `#[target_feature(enable = ...)]` attribute. It also adds a note about a conflict between `e` and `h` (no code changes for now but should be rejected in the future). --- compiler/rustc_target/src/target_features.rs | 5 +++++ tests/ui/check-cfg/target_feature.stderr | 2 ++ 2 files changed, 7 insertions(+) diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index dc70089c385fe..fc824e4231e30 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -599,6 +599,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ Stability::Forbidden { reason: "unsound because it changes the ABI of atomic operations" }, &[], ), + ("h", Unstable(sym::riscv_target_feature), &["zicsr"]), ("m", Stable, &[]), ("relax", Unstable(sym::riscv_target_feature), &[]), ( @@ -644,6 +645,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ ], ), ("supm", Unstable(sym::riscv_target_feature), &[]), + ("svinval", Unstable(sym::riscv_target_feature), &[]), ("unaligned-scalar-mem", Unstable(sym::riscv_target_feature), &[]), ("unaligned-vector-mem", Unstable(sym::riscv_target_feature), &[]), ("v", Unstable(sym::riscv_target_feature), &["zvl128b", "zve64d"]), @@ -1147,6 +1149,9 @@ impl Target { // Note that the `e` feature is not required: the ABI treats the extra // registers as caller-save, so it is safe to use them only in some parts of // a program while the rest doesn't know they even exist. + // For the same reason, this ABI is *not* stated incompatible with `h`, + // which requires a base integer ISA with 32 general purpose registers + // and is incompatible with the `e` feature. FeatureConstraints { required: &[], incompatible: &["d"] } } "lp64e" => { diff --git a/tests/ui/check-cfg/target_feature.stderr b/tests/ui/check-cfg/target_feature.stderr index 258f21324661b..a82472710d20c 100644 --- a/tests/ui/check-cfg/target_feature.stderr +++ b/tests/ui/check-cfg/target_feature.stderr @@ -124,6 +124,7 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE"); `fxsr` `gfni` `guarded-storage` +`h` `hard-float` `hard-float-abi` `hard-tp` @@ -314,6 +315,7 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE"); `sve2-sha3` `sve2-sm4` `sve2p1` +`svinval` `tail-call` `tbm` `thumb-mode`