@@ -93,38 +93,32 @@ pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
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_ if intrinsic. starts_with ( "llvm.aarch64.neon.fmax.v" ) => {
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intrinsic_args ! ( fx, args => ( x, y) ; intrinsic) ;
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-
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+
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simd_pair_for_each_lane (
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fx,
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x,
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y,
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ret,
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- & |fx, _lane_ty, _res_lane_ty, x_lane, y_lane| {
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- fx. bcx . ins ( ) . fmax ( x_lane, y_lane)
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- }
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+ & |fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx. bcx . ins ( ) . fmax ( x_lane, y_lane) ,
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) ;
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}
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_ if intrinsic. starts_with ( "llvm.aarch64.neon.fmin.v" ) => {
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intrinsic_args ! ( fx, args => ( x, y) ; intrinsic) ;
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-
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+
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simd_pair_for_each_lane (
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fx,
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x,
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y,
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ret,
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- & |fx, _lane_ty, _res_lane_ty, x_lane, y_lane| {
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- fx. bcx . ins ( ) . fmin ( x_lane, y_lane)
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- }
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+ & |fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx. bcx . ins ( ) . fmin ( x_lane, y_lane) ,
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) ;
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}
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_ if intrinsic. starts_with ( "llvm.aarch64.neon.faddv.f32.v" ) => {
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intrinsic_args ! ( fx, args => ( v) ; intrinsic) ;
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- simd_reduce ( fx, v, None , ret, & |fx, _ty, a, b| {
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- fx. bcx . ins ( ) . fadd ( a, b)
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- } ) ;
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+ simd_reduce ( fx, v, None , ret, & |fx, _ty, a, b| fx. bcx . ins ( ) . fadd ( a, b) ) ;
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}
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_ if intrinsic. starts_with ( "llvm.aarch64.neon.frintn.v" ) => {
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