RISC-V: tidying: Handling of base ISA

This commit makes handling of the base ISA a separate block.

Co-Authored-By: Taiki Endo <[email protected]>

Author: a4lg

crates/std_detect/src/detect/os/linux/riscv.rs

@@ -44,28 +44,32 @@ pub(crate) fn detect_features() -> cache::Initializer {
         &[Feature::f, Feature::zicsr],
         bit::test(auxv.hwcap, (b'f' - b'a').into()),
     );
+    enable_feature(
+        &mut value,
+        Feature::h,
+        bit::test(auxv.hwcap, (b'h' - b'a').into()),
+    );
+    enable_feature(
+        &mut value,
+        Feature::m,
+        bit::test(auxv.hwcap, (b'm' - b'a').into()),
+    );
+
+    // Handle base ISA.
     let has_i = bit::test(auxv.hwcap, (b'i' - b'a').into());
     // If future RV128I is supported, implement with `enable_feature` here
     #[cfg(target_pointer_width = "64")]
     enable_feature(&mut value, Feature::rv64i, has_i);
     #[cfg(target_pointer_width = "32")]
     enable_feature(&mut value, Feature::rv32i, has_i);
+    // FIXME: e is not exposed in any of asm/hwcap.h, uapi/asm/hwcap.h, uapi/asm/hwprobe.h
     #[cfg(target_pointer_width = "32")]
     enable_feature(
         &mut value,
         Feature::rv32e,
         bit::test(auxv.hwcap, (b'e' - b'a').into()),
     );
-    enable_feature(
-        &mut value,
-        Feature::h,
-        bit::test(auxv.hwcap, (b'h' - b'a').into()),
-    );
-    enable_feature(
-        &mut value,
-        Feature::m,
-        bit::test(auxv.hwcap, (b'm' - b'a').into()),
-    );
+
     // FIXME: Auxvec does not show supervisor feature support, but this mode may be useful
     // to detect when Rust is used to write Linux kernel modules.
     // These should be more than Auxvec way to detect supervisor features.