@@ -1548,7 +1548,7 @@ pub unsafe fn vld1q_s8(addr: *const i8) -> int8x16_t {
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* ( addr as * const int8x16_t )
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}
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- // int8x16_t vld1q_s8 (int8_t const * ptr)
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+ /// int8x16_t vld1q_s8 (int8_t const * ptr)
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#[ inline]
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#[ target_feature( enable = "neon" ) ]
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#[ cfg_attr( target_arch = "arm" , target_feature( enable = "v7" ) ) ]
@@ -1557,6 +1557,15 @@ pub unsafe fn vld1q_u8(addr: *const u8) -> uint8x16_t {
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* ( addr as * const uint8x16_t )
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}
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+ /// void vst1q_u8 (uint8_t * ptr, uint8x16_t val)
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+ #[ inline]
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+ #[ target_feature( enable = "neon" ) ]
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+ #[ cfg_attr( target_arch = "arm" , target_feature( enable = "v7" ) ) ]
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+ #[ cfg_attr( test, assert_instr( st1) ) ]
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+ pub unsafe fn vst1q_u8 ( addr : * mut u8 , val : uint8x16_t ) {
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+ ptr:: write ( addr as * mut uint8x16_t , val) ;
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+ }
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+
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macro_rules! arm_reinterpret {
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( $name: ident, $from: ty, $to: ty) => {
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// Vector reinterpret cast operation
@@ -1767,6 +1776,15 @@ mod tests {
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assert_eq ! ( r, e) ;
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}
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+ #[ simd_test( enable = "neon" ) ]
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+ unsafe fn test_vst1q_u8 ( ) {
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+ let a = u8x16:: new ( 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 ) ;
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+ let e = a;
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+ let mut r = u8x16:: new ( 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ) ;
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+ vst1q_u8 ( transmute ( & mut r) , transmute ( a) ) ;
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+ assert_eq ! ( r, e) ;
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+ }
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+
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#[ simd_test( enable = "neon" ) ]
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unsafe fn test_vreinterpret_u64_u32 ( ) {
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let v: i8 = 42 ;
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