@@ -21417,14 +21417,7 @@ pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2141721417#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2141821418#[cfg_attr(test, assert_instr(rbit))]
2141921419pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
21420- unsafe extern "unadjusted" {
21421- #[cfg_attr(
21422- any(target_arch = "aarch64", target_arch = "arm64ec"),
21423- link_name = "llvm.bitreverse.v8i8"
21424- )]
21425- fn _vrbit_s8(a: int8x8_t) -> int8x8_t;
21426- }
21427- unsafe { _vrbit_s8(a) }
21420+ unsafe { simd_bitreverse(a) }
2142821421}
2142921422#[doc = "Reverse bit order"]
2143021423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"]
@@ -21433,14 +21426,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
2143321426#[stable(feature = "neon_intrinsics", since = "1.59.0")]
2143421427#[cfg_attr(test, assert_instr(rbit))]
2143521428pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
21436- unsafe extern "unadjusted" {
21437- #[cfg_attr(
21438- any(target_arch = "aarch64", target_arch = "arm64ec"),
21439- link_name = "llvm.bitreverse.v16i8"
21440- )]
21441- fn _vrbitq_s8(a: int8x16_t) -> int8x16_t;
21442- }
21443- unsafe { _vrbitq_s8(a) }
21429+ unsafe { simd_bitreverse(a) }
2144421430}
2144521431#[doc = "Reverse bit order"]
2144621432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
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