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Remove workarounds for rust-lang/rust#60637 
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4 files changed

+48
-78
lines changed

4 files changed

+48
-78
lines changed

‎crates/core_arch/src/arm_shared/neon/generated.rs‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -10594,7 +10594,7 @@ pub fn vdupq_n_f16(a: f16) -> float16x8_t {
1059410594
#[inline]
1059510595
#[target_feature(enable = "neon")]
1059610596
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10597-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10597+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1059810598
#[cfg_attr(
1059910599
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1060010600
assert_instr(dup)
@@ -10615,7 +10615,7 @@ pub fn vdup_n_f32(value: f32) -> float32x2_t {
1061510615
#[inline]
1061610616
#[target_feature(enable = "neon")]
1061710617
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10618-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10618+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1061910619
#[cfg_attr(
1062010620
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1062110621
assert_instr(dup)
@@ -10636,7 +10636,7 @@ pub fn vdup_n_p16(value: p16) -> poly16x4_t {
1063610636
#[inline]
1063710637
#[target_feature(enable = "neon")]
1063810638
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10639-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10639+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1064010640
#[cfg_attr(
1064110641
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1064210642
assert_instr(dup)
@@ -10657,7 +10657,7 @@ pub fn vdup_n_p8(value: p8) -> poly8x8_t {
1065710657
#[inline]
1065810658
#[target_feature(enable = "neon")]
1065910659
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10660-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10660+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1066110661
#[cfg_attr(
1066210662
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1066310663
assert_instr(dup)
@@ -10678,7 +10678,7 @@ pub fn vdup_n_s16(value: i16) -> int16x4_t {
1067810678
#[inline]
1067910679
#[target_feature(enable = "neon")]
1068010680
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10681-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10681+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1068210682
#[cfg_attr(
1068310683
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1068410684
assert_instr(dup)
@@ -10699,7 +10699,7 @@ pub fn vdup_n_s32(value: i32) -> int32x2_t {
1069910699
#[inline]
1070010700
#[target_feature(enable = "neon")]
1070110701
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10702-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10702+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1070310703
#[cfg_attr(
1070410704
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1070510705
assert_instr(fmov)
@@ -10720,7 +10720,7 @@ pub fn vdup_n_s64(value: i64) -> int64x1_t {
1072010720
#[inline]
1072110721
#[target_feature(enable = "neon")]
1072210722
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10723-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10723+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1072410724
#[cfg_attr(
1072510725
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1072610726
assert_instr(dup)
@@ -10741,7 +10741,7 @@ pub fn vdup_n_s8(value: i8) -> int8x8_t {
1074110741
#[inline]
1074210742
#[target_feature(enable = "neon")]
1074310743
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10744-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10744+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1074510745
#[cfg_attr(
1074610746
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1074710747
assert_instr(dup)
@@ -10762,7 +10762,7 @@ pub fn vdup_n_u16(value: u16) -> uint16x4_t {
1076210762
#[inline]
1076310763
#[target_feature(enable = "neon")]
1076410764
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10765-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10765+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1076610766
#[cfg_attr(
1076710767
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1076810768
assert_instr(dup)
@@ -10783,7 +10783,7 @@ pub fn vdup_n_u32(value: u32) -> uint32x2_t {
1078310783
#[inline]
1078410784
#[target_feature(enable = "neon")]
1078510785
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10786-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10786+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1078710787
#[cfg_attr(
1078810788
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1078910789
assert_instr(fmov)
@@ -10804,7 +10804,7 @@ pub fn vdup_n_u64(value: u64) -> uint64x1_t {
1080410804
#[inline]
1080510805
#[target_feature(enable = "neon")]
1080610806
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10807-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10807+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
1080810808
#[cfg_attr(
1080910809
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1081010810
assert_instr(dup)
@@ -31909,7 +31909,7 @@ pub fn vmovq_n_f16(a: f16) -> float16x8_t {
3190931909
#[inline]
3191031910
#[target_feature(enable = "neon")]
3191131911
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31912-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31912+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3191331913
#[cfg_attr(
3191431914
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3191531915
assert_instr(dup)
@@ -31930,7 +31930,7 @@ pub fn vmov_n_f32(value: f32) -> float32x2_t {
3193031930
#[inline]
3193131931
#[target_feature(enable = "neon")]
3193231932
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31933-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31933+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3193431934
#[cfg_attr(
3193531935
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3193631936
assert_instr(dup)
@@ -31951,7 +31951,7 @@ pub fn vmov_n_p16(value: p16) -> poly16x4_t {
3195131951
#[inline]
3195231952
#[target_feature(enable = "neon")]
3195331953
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31954-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31954+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3195531955
#[cfg_attr(
3195631956
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3195731957
assert_instr(dup)
@@ -31972,7 +31972,7 @@ pub fn vmov_n_p8(value: p8) -> poly8x8_t {
3197231972
#[inline]
3197331973
#[target_feature(enable = "neon")]
3197431974
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31975-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31975+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3197631976
#[cfg_attr(
3197731977
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3197831978
assert_instr(dup)
@@ -31993,7 +31993,7 @@ pub fn vmov_n_s16(value: i16) -> int16x4_t {
3199331993
#[inline]
3199431994
#[target_feature(enable = "neon")]
3199531995
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31996-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31996+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3199731997
#[cfg_attr(
3199831998
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3199931999
assert_instr(dup)
@@ -32014,7 +32014,7 @@ pub fn vmov_n_s32(value: i32) -> int32x2_t {
3201432014
#[inline]
3201532015
#[target_feature(enable = "neon")]
3201632016
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32017-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32017+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3201832018
#[cfg_attr(
3201932019
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3202032020
assert_instr(fmov)
@@ -32035,7 +32035,7 @@ pub fn vmov_n_s64(value: i64) -> int64x1_t {
3203532035
#[inline]
3203632036
#[target_feature(enable = "neon")]
3203732037
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32038-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32038+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3203932039
#[cfg_attr(
3204032040
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3204132041
assert_instr(dup)
@@ -32056,7 +32056,7 @@ pub fn vmov_n_s8(value: i8) -> int8x8_t {
3205632056
#[inline]
3205732057
#[target_feature(enable = "neon")]
3205832058
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32059-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32059+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3206032060
#[cfg_attr(
3206132061
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3206232062
assert_instr(dup)
@@ -32077,7 +32077,7 @@ pub fn vmov_n_u16(value: u16) -> uint16x4_t {
3207732077
#[inline]
3207832078
#[target_feature(enable = "neon")]
3207932079
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32080-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32080+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3208132081
#[cfg_attr(
3208232082
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3208332083
assert_instr(dup)
@@ -32098,7 +32098,7 @@ pub fn vmov_n_u32(value: u32) -> uint32x2_t {
3209832098
#[inline]
3209932099
#[target_feature(enable = "neon")]
3210032100
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32101-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32101+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3210232102
#[cfg_attr(
3210332103
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3210432104
assert_instr(fmov)
@@ -32119,7 +32119,7 @@ pub fn vmov_n_u64(value: u64) -> uint64x1_t {
3211932119
#[inline]
3212032120
#[target_feature(enable = "neon")]
3212132121
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32122-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32122+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("nop"))]
3212332123
#[cfg_attr(
3212432124
all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3212532125
assert_instr(dup)

‎crates/core_arch/src/macros.rs‎

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -94,25 +94,15 @@ macro_rules! types {
9494
/// so use this internal helper for it instead.
9595
#[inline(always)]
9696
$v fn splat(value: $elem_type) -> $name {
97-
#[derive(Copy, Clone)]
98-
#[repr(simd)]
99-
struct JustOne([$elem_type; 1]);
100-
let one = JustOne([value]);
101-
// SAFETY: 0 is always in-bounds because we're shuffling
102-
// a simd type with exactly one element.
103-
unsafe { simd_shuffle!(one, one, [0; $len]) }
97+
$name([value; $len])
10498
}
10599

106100
/// Returns an array reference containing the entire SIMD vector.
107101
$v const fn as_array(&self) -> &[$elem_type; $len] {
108102
// SAFETY: this type is just an overaligned `[T; N]` with
109103
// potential padding at the end, so pointer casting to a
110104
// `&[T; N]` is safe.
111-
//
112-
// NOTE: This deliberately doesn't just use `&self.0` because it may soon be banned
113-
// see https://github.com/rust-lang/compiler-team/issues/838
114105
unsafe { &*(self as *const Self as *const [$elem_type; $len]) }
115-
116106
}
117107

118108
/// Returns a mutable array reference containing the entire SIMD vector.
@@ -121,9 +111,6 @@ macro_rules! types {
121111
// SAFETY: this type is just an overaligned `[T; N]` with
122112
// potential padding at the end, so pointer casting to a
123113
// `&mut [T; N]` is safe.
124-
//
125-
// NOTE: This deliberately doesn't just use `&mut self.0` because it may soon be banned
126-
// see https://github.com/rust-lang/compiler-team/issues/838
127114
unsafe { &mut *(self as *mut Self as *mut [$elem_type; $len]) }
128115
}
129116
}

‎crates/core_arch/src/simd.rs‎

Lines changed: 3 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -21,22 +21,12 @@ macro_rules! simd_ty {
2121
pub(crate) const fn from_array(elements: [$elem_type; $len]) -> Self {
2222
$id(elements)
2323
}
24-
// FIXME: Workaround rust@60637
24+
2525
#[inline(always)]
2626
pub(crate) fn splat(value: $elem_type) -> Self {
27-
#[derive(Copy, Clone)]
28-
#[repr(simd)]
29-
struct JustOne([$elem_type; 1]);
30-
let one = JustOne([value]);
31-
// SAFETY: 0 is always in-bounds because we're shuffling
32-
// a simd type with exactly one element.
33-
unsafe { simd_shuffle!(one, one, [0; $len]) }
27+
$id([value; $len])
3428
}
3529

36-
/// Extract the element at position `index`.
37-
/// `index` is not a constant so this is not efficient!
38-
/// Use for testing only.
39-
// FIXME: Workaround rust@60637
4030
#[inline(always)]
4131
pub(crate) fn extract(&self, index: usize) -> $elem_type {
4232
self.as_array()[index]
@@ -87,16 +77,9 @@ macro_rules! simd_m_ty {
8777
$id([$(Self::bool_to_internal($param_name)),*])
8878
}
8979

90-
// FIXME: Workaround rust@60637
9180
#[inline(always)]
9281
pub(crate) fn splat(value: bool) -> Self {
93-
#[derive(Copy, Clone)]
94-
#[repr(simd)]
95-
struct JustOne([$elem_type; 1]);
96-
let one = JustOne([Self::bool_to_internal(value)]);
97-
// SAFETY: 0 is always in-bounds because we're shuffling
98-
// a simd type with exactly one element.
99-
unsafe { simd_shuffle!(one, one, [0; $len]) }
82+
$id([Self::bool_to_internal(value); $len])
10083
}
10184

10285
#[inline]

‎crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -14939,17 +14939,17 @@ intrinsics:
1493914939
- ['vdupq_n_u64', 'u64', 'uint64x2_t', 'vmov', 'dup', 'uint64x2_t::splat(value)']
1494014940
- ['vdupq_n_p8', 'u8', 'poly8x16_t', 'vdup.8', 'dup', 'poly8x16_t::splat(value)']
1494114941
- ['vdupq_n_p16', 'p16', 'poly16x8_t', 'vdup.16', 'dup', 'poly16x8_t::splat(value)']
14942-
- ['vdup_n_s8', 'i8', 'int8x8_t', 'vdup.8', 'dup', 'int8x8_t::splat(value)']
14943-
- ['vdup_n_s16', 'i16', 'int16x4_t', 'vdup.16', 'dup', 'int16x4_t::splat(value)']
14944-
- ['vdup_n_s32', 'i32', 'int32x2_t', 'vdup.32', 'dup', 'int32x2_t::splat(value)']
14945-
- ['vdup_n_s64', 'i64', 'int64x1_t', 'vmov', 'fmov', 'int64x1_t::splat(value)']
14946-
- ['vdup_n_u8', 'u8', 'uint8x8_t', 'vdup.8', 'dup', 'uint8x8_t::splat(value)']
14947-
- ['vdup_n_u16', 'u16', 'uint16x4_t', 'vdup.16', 'dup', 'uint16x4_t::splat(value)']
14948-
- ['vdup_n_u32', 'u32', 'uint32x2_t', 'vdup.32', 'dup', 'uint32x2_t::splat(value)']
14949-
- ['vdup_n_f32', 'f32', 'float32x2_t', 'vdup.32', 'dup', 'float32x2_t::splat(value)']
14950-
- ['vdup_n_u64', 'u64', 'uint64x1_t', 'vmov', 'fmov', 'uint64x1_t::splat(value)']
14951-
- ['vdup_n_p8', 'p8', 'poly8x8_t', 'vdup.8', 'dup', 'poly8x8_t::splat(value)']
14952-
- ['vdup_n_p16', 'p16', 'poly16x4_t', 'vdup.16', 'dup', 'poly16x4_t::splat(value)']
14942+
- ['vdup_n_s8', 'i8', 'int8x8_t', 'nop', 'dup', 'int8x8_t::splat(value)']
14943+
- ['vdup_n_s16', 'i16', 'int16x4_t', 'nop', 'dup', 'int16x4_t::splat(value)']
14944+
- ['vdup_n_s32', 'i32', 'int32x2_t', 'nop', 'dup', 'int32x2_t::splat(value)']
14945+
- ['vdup_n_s64', 'i64', 'int64x1_t', 'nop', 'fmov', 'int64x1_t::splat(value)']
14946+
- ['vdup_n_u8', 'u8', 'uint8x8_t', 'nop', 'dup', 'uint8x8_t::splat(value)']
14947+
- ['vdup_n_u16', 'u16', 'uint16x4_t', 'nop', 'dup', 'uint16x4_t::splat(value)']
14948+
- ['vdup_n_u32', 'u32', 'uint32x2_t', 'nop', 'dup', 'uint32x2_t::splat(value)']
14949+
- ['vdup_n_f32', 'f32', 'float32x2_t', 'nop', 'dup', 'float32x2_t::splat(value)']
14950+
- ['vdup_n_u64', 'u64', 'uint64x1_t', 'nop', 'fmov', 'uint64x1_t::splat(value)']
14951+
- ['vdup_n_p8', 'p8', 'poly8x8_t', 'nop', 'dup', 'poly8x8_t::splat(value)']
14952+
- ['vdup_n_p16', 'p16', 'poly16x4_t', 'nop', 'dup', 'poly16x4_t::splat(value)']
1495314953
compose:
1495414954
- Identifier: ['{type[5]}', Symbol]
1495514955

@@ -14965,17 +14965,17 @@ intrinsics:
1496514965
- *neon-cfg-arm-unstable
1496614966
safety: safe
1496714967
types:
14968-
- ['vmov_n_s8', 'i8', 'int8x8_t', 'vdup.8', 'dup', 'vdup_n_s8']
14969-
- ['vmov_n_s16', 'i16', 'int16x4_t', 'vdup.16', 'dup', 'vdup_n_s16']
14970-
- ['vmov_n_s32', 'i32', 'int32x2_t', 'vdup.32', 'dup', 'vdup_n_s32']
14971-
- ['vmov_n_s64', 'i64', 'int64x1_t', 'vmov', 'fmov', 'vdup_n_s64']
14972-
- ['vmov_n_u8', 'u8', 'uint8x8_t', 'vdup.8', 'dup', 'vdup_n_u8']
14973-
- ['vmov_n_u16', 'u16', 'uint16x4_t', 'vdup.16', 'dup', 'vdup_n_u16']
14974-
- ['vmov_n_u32', 'u32', 'uint32x2_t', 'vdup.32', 'dup', 'vdup_n_u32']
14975-
- ['vmov_n_u64', 'u64', 'uint64x1_t', 'vmov', 'fmov', 'vdup_n_u64']
14976-
- ['vmov_n_p8', 'p8', 'poly8x8_t', 'vdup.8', 'dup', 'vdup_n_p8']
14977-
- ['vmov_n_p16', 'p16', 'poly16x4_t', 'vdup.16', 'dup', 'vdup_n_p16']
14978-
- ['vmov_n_f32', 'f32', 'float32x2_t', 'vdup.32', 'dup', 'vdup_n_f32']
14968+
- ['vmov_n_s8', 'i8', 'int8x8_t', 'nop', 'dup', 'vdup_n_s8']
14969+
- ['vmov_n_s16', 'i16', 'int16x4_t', 'nop', 'dup', 'vdup_n_s16']
14970+
- ['vmov_n_s32', 'i32', 'int32x2_t', 'nop', 'dup', 'vdup_n_s32']
14971+
- ['vmov_n_s64', 'i64', 'int64x1_t', 'nop', 'fmov', 'vdup_n_s64']
14972+
- ['vmov_n_u8', 'u8', 'uint8x8_t', 'nop', 'dup', 'vdup_n_u8']
14973+
- ['vmov_n_u16', 'u16', 'uint16x4_t', 'nop', 'dup', 'vdup_n_u16']
14974+
- ['vmov_n_u32', 'u32', 'uint32x2_t', 'nop', 'dup', 'vdup_n_u32']
14975+
- ['vmov_n_u64', 'u64', 'uint64x1_t', 'nop', 'fmov', 'vdup_n_u64']
14976+
- ['vmov_n_p8', 'p8', 'poly8x8_t', 'nop', 'dup', 'vdup_n_p8']
14977+
- ['vmov_n_p16', 'p16', 'poly16x4_t', 'nop', 'dup', 'vdup_n_p16']
14978+
- ['vmov_n_f32', 'f32', 'float32x2_t', 'nop', 'dup', 'vdup_n_f32']
1497914979
- ['vmovq_n_s8', 'i8', 'int8x16_t', 'vdup.8', 'dup', 'vdupq_n_s8']
1498014980
- ['vmovq_n_s16', 'i16', 'int16x8_t', 'vdup.16', 'dup', 'vdupq_n_s16']
1498114981
- ['vmovq_n_s32', 'i32', 'int32x4_t', 'vdup.32', 'dup', 'vdupq_n_s32']

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