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use simd_bitreverse on aarch64 #1815

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Merged
merged 1 commit into from
Jun 1, 2025
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use simd_bitreverse on aarch64 #1815

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18 changes: 2 additions & 16 deletions crates/core_arch/src/aarch64/neon/generated.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21417,14 +21417,7 @@ pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(rbit))]
pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.bitreverse.v8i8"
)]
fn _vrbit_s8(a: int8x8_t) -> int8x8_t;
}
unsafe { _vrbit_s8(a) }
unsafe { simd_bitreverse(a) }
}
#[doc = "Reverse bit order"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"]
Expand All @@ -21433,14 +21426,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(rbit))]
pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.bitreverse.v16i8"
)]
fn _vrbitq_s8(a: int8x16_t) -> int8x16_t;
}
unsafe { _vrbitq_s8(a) }
unsafe { simd_bitreverse(a) }
}
#[doc = "Reverse bit order"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
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8 changes: 3 additions & 5 deletions crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
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Expand Up @@ -2940,11 +2940,9 @@ intrinsics:
- int8x8_t
- int8x16_t
compose:
- LLVMLink:
name: "rbit.{neon_type}"
links:
- link: "llvm.bitreverse.{neon_type}"
arch: aarch64,arm64ec
- FnCall:
- simd_bitreverse
- - a

- name: "vrbit{neon_type[0].no}"
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Contributor Author

@folkertdev folkertdev May 30, 2025

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it seems possible to use simd_bitreverse here too, but I can't get it to generate the right thing.

doc: Reverse bit order
Expand Down