Skip to content

Commit 09b195d

Browse files
Radu-VoineaRadu-Voinea
committed
Reformatted respecting cargo fmt --all
1 parent 9279f36 commit 09b195d

File tree

4 files changed

+98
-90
lines changed

4 files changed

+98
-90
lines changed

‎docs/apic_example/src/apic.rs

Lines changed: 79 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -16,70 +16,70 @@ lazy_static! {
1616
#[repr(isize)]
1717
#[allow(dead_code)]
1818
pub enum APICOffset {
19-
// RESERVED = 0x00
20-
// RESERVED = 0x10
21-
Ir = 0x20, // ID Register
22-
Vr = 0x30, // Version Register
23-
// RESERVED = 0x40
24-
// RESERVED = 0x50
25-
// RESERVED = 0x60
26-
// RESERVED = 0x70
27-
Tpr = 0x80, // Text Priority Register
28-
Apr = 0x90, // Arbitration Priority Register
29-
Ppr = 0xA0, // Processor Priority Register
30-
Eoi = 0xB0, // End of Interrupt
31-
Rrd = 0xC0, // Remote Read Register
32-
Ldr = 0xD0, // Logical Destination Register
33-
Dfr = 0xE0, // DFR
34-
Svr = 0xF0, // Spurious (Interrupt) Vector Register
35-
Isr1 = 0x100, // In-Service Register 1
36-
Isr2 = 0x110, // In-Service Register 2
37-
Isr3 = 0x120, // In-Service Register 3
38-
Isr4 = 0x130, // In-Service Register 4
39-
Isr5 = 0x140, // In-Service Register 5
40-
Isr6 = 0x150, // In-Service Register 6
41-
Isr7 = 0x160, // In-Service Register 7
42-
Isr8 = 0x170, // In-Service Register 8
43-
Tmr1 = 0x180, // Trigger Mode Register 1
44-
Tmr2 = 0x190, // Trigger Mode Register 2
45-
Tmr3 = 0x1A0, // Trigger Mode Register 3
46-
Tmr4 = 0x1B0, // Trigger Mode Register 4
47-
Tmr5 = 0x1C0, // Trigger Mode Register 5
48-
Tmr6 = 0x1D0, // Trigger Mode Register 6
49-
Tmr7 = 0x1E0, // Trigger Mode Register 7
50-
Tmr8 = 0x1F0, // Trigger Mode Register 8
51-
Irr1 = 0x200, // Interrupt Request Register 1
52-
Irr2 = 0x210, // Interrupt Request Register 2
53-
Irr3 = 0x220, // Interrupt Request Register 3
54-
Irr4 = 0x230, // Interrupt Request Register 4
55-
Irr5 = 0x240, // Interrupt Request Register 5
56-
Irr6 = 0x250, // Interrupt Request Register 6
57-
Irr7 = 0x260, // Interrupt Request Register 7
58-
Irr8 = 0x270, // Interrupt Request Register 8
59-
Esr = 0x280, // Error Status Register
60-
// RESERVED = 0x290
61-
// RESERVED = 0x2A0
62-
// RESERVED = 0x2B0
63-
// RESERVED = 0x2C0
64-
// RESERVED = 0x2D0
65-
// RESERVED = 0x2E0
66-
LvtCmci = 0x2F0, // LVT Corrected Machine Check Interrupt (CMCI) Register
67-
Icr1 = 0x300, // Interrupt Command Register 1
68-
Icr2 = 0x310, // Interrupt Command Register 2
69-
LvtT = 0x320, // LVT Timer Register
70-
LvtTsr = 0x330, // LVT Thermal Sensor Register
71-
LvtPmcr = 0x340, // LVT Performance Monitoring Counters Register
19+
R0x00 = 0x0, // RESERVED = 0x00
20+
R0x10 = 0x10, // RESERVED = 0x10
21+
Ir = 0x20, // ID Register
22+
Vr = 0x30, // Version Register
23+
R0x40 = 0x40, // RESERVED = 0x40
24+
R0x50 = 0x50, // RESERVED = 0x50
25+
R0x60 = 0x60, // RESERVED = 0x60
26+
R0x70 = 0x70, // RESERVED = 0x70
27+
Tpr = 0x80, // Text Priority Register
28+
Apr = 0x90, // Arbitration Priority Register
29+
Ppr = 0xA0, // Processor Priority Register
30+
Eoi = 0xB0, // End of Interrupt
31+
Rrd = 0xC0, // Remote Read Register
32+
Ldr = 0xD0, // Logical Destination Register
33+
Dfr = 0xE0, // DFR
34+
Svr = 0xF0, // Spurious (Interrupt) Vector Register
35+
Isr1 = 0x100, // In-Service Register 1
36+
Isr2 = 0x110, // In-Service Register 2
37+
Isr3 = 0x120, // In-Service Register 3
38+
Isr4 = 0x130, // In-Service Register 4
39+
Isr5 = 0x140, // In-Service Register 5
40+
Isr6 = 0x150, // In-Service Register 6
41+
Isr7 = 0x160, // In-Service Register 7
42+
Isr8 = 0x170, // In-Service Register 8
43+
Tmr1 = 0x180, // Trigger Mode Register 1
44+
Tmr2 = 0x190, // Trigger Mode Register 2
45+
Tmr3 = 0x1A0, // Trigger Mode Register 3
46+
Tmr4 = 0x1B0, // Trigger Mode Register 4
47+
Tmr5 = 0x1C0, // Trigger Mode Register 5
48+
Tmr6 = 0x1D0, // Trigger Mode Register 6
49+
Tmr7 = 0x1E0, // Trigger Mode Register 7
50+
Tmr8 = 0x1F0, // Trigger Mode Register 8
51+
Irr1 = 0x200, // Interrupt Request Register 1
52+
Irr2 = 0x210, // Interrupt Request Register 2
53+
Irr3 = 0x220, // Interrupt Request Register 3
54+
Irr4 = 0x230, // Interrupt Request Register 4
55+
Irr5 = 0x240, // Interrupt Request Register 5
56+
Irr6 = 0x250, // Interrupt Request Register 6
57+
Irr7 = 0x260, // Interrupt Request Register 7
58+
Irr8 = 0x270, // Interrupt Request Register 8
59+
Esr = 0x280, // Error Status Register
60+
R0x290 = 0x290, // RESERVED = 0x290
61+
R0x2A0 = 0x2A0, // RESERVED = 0x2A0
62+
R0x2B0 = 0x2B0, // RESERVED = 0x2B0
63+
R0x2C0 = 0x2C0, // RESERVED = 0x2C0
64+
R0x2D0 = 0x2D0, // RESERVED = 0x2D0
65+
R0x2E0 = 0x2E0, // RESERVED = 0x2E0
66+
LvtCmci = 0x2F0, // LVT Corrected Machine Check Interrupt (CMCI) Register
67+
Icr1 = 0x300, // Interrupt Command Register 1
68+
Icr2 = 0x310, // Interrupt Command Register 2
69+
LvtT = 0x320, // LVT Timer Register
70+
LvtTsr = 0x330, // LVT Thermal Sensor Register
71+
LvtPmcr = 0x340, // LVT Performance Monitoring Counters Register
7272
LvtLint0 = 0x350, // LVT LINT0 Register
7373
LvtLint1 = 0x360, // LVT LINT1 Register
74-
LvtE = 0x370, // LVT Error Register
75-
Ticr = 0x380, // Initial Count Register (for Timer)
76-
Tccr = 0x390, // Current Count Register (for Timer)
77-
// RESERVED = 0x3A0
78-
// RESERVED = 0x3B0
79-
// RESERVED = 0x3C0
80-
// RESERVED = 0x3D0
81-
Tdcr = 0x3E0, // Divide Configuration Register (for Timer)
82-
// RESERVED = 0x3F0
74+
LvtE = 0x370, // LVT Error Register
75+
Ticr = 0x380, // Initial Count Register (for Timer)
76+
Tccr = 0x390, // Current Count Register (for Timer)
77+
R0x3A0 = 0x3A0, // RESERVED = 0x3A0
78+
R0x3B0 = 0x3B0, // RESERVED = 0x3B0
79+
R0x3C0 = 0x3C0, // RESERVED = 0x3C0
80+
R0x3D0 = 0x3D0, // RESERVED = 0x3D0
81+
Tdcr = 0x3E0, // Divide Configuration Register (for Timer)
82+
R0x3F0 = 0x3F0, // RESERVED = 0x3F0
8383
}
8484

8585
pub struct LAPICAddress {
@@ -92,7 +92,7 @@ unsafe impl Sync for LAPICAddress {}
9292
impl LAPICAddress {
9393
pub fn new() -> Self {
9494
Self {
95-
address: core::ptr::null_mut()
95+
address: core::ptr::null_mut(),
9696
}
9797
}
9898
}
@@ -103,7 +103,9 @@ pub struct AcpiHandlerImpl {
103103

104104
impl AcpiHandlerImpl {
105105
pub fn new(physical_memory_offset: VirtAddr) -> Self {
106-
Self { physical_memory_offset }
106+
Self {
107+
physical_memory_offset,
108+
}
107109
}
108110
}
109111

@@ -142,13 +144,16 @@ impl AcpiHandler for AcpiHandlerImpl {
142144
}
143145

144146
pub unsafe fn init(
145-
rsdp: usize, physical_memory_offset: VirtAddr,
147+
rsdp: usize,
148+
physical_memory_offset: VirtAddr,
146149
mapper: &mut impl Mapper<Size4KiB>,
147150
frame_allocator: &mut impl FrameAllocator<Size4KiB>,
148151
) {
149152
let handler = AcpiHandlerImpl::new(physical_memory_offset);
150153
let acpi_tables = AcpiTables::from_rsdp(handler, rsdp).expect("Failed to parse ACPI tables");
151-
let platform_info = acpi_tables.platform_info().expect("Failed to get platform info");
154+
let platform_info = acpi_tables
155+
.platform_info()
156+
.expect("Failed to get platform info");
152157
match platform_info.interrupt_model {
153158
acpi::InterruptModel::Apic(apic) => {
154159
let io_apic_address = apic.io_apics[0].address;
@@ -173,11 +178,7 @@ unsafe fn init_local_apic(
173178
mapper: &mut impl Mapper<Size4KiB>,
174179
frame_allocator: &mut impl FrameAllocator<Size4KiB>,
175180
) {
176-
let virtual_address = map_apic(
177-
local_apic_addr as u64,
178-
mapper,
179-
frame_allocator,
180-
);
181+
let virtual_address = map_apic(local_apic_addr as u64, mapper, frame_allocator);
181182

182183
let lapic_pointer = virtual_address.as_mut_ptr::<u32>();
183184
LAPIC_ADDR.lock().address = lapic_pointer;
@@ -210,19 +211,16 @@ unsafe fn init_io_apic(
210211
mapper: &mut impl Mapper<Size4KiB>,
211212
frame_allocator: &mut impl FrameAllocator<Size4KiB>,
212213
) {
213-
let virt_addr = map_apic(
214-
ioapic_address as u64,
215-
mapper,
216-
frame_allocator,
217-
);
214+
let virt_addr = map_apic(ioapic_address as u64, mapper, frame_allocator);
218215

219216
let ioapic_pointer = virt_addr.as_mut_ptr::<u32>();
220217

221218
ioapic_pointer.offset(0).write_volatile(0x12);
222-
ioapic_pointer.offset(4).write_volatile(InterruptIndex::Keyboard as u8 as u32);
219+
ioapic_pointer
220+
.offset(4)
221+
.write_volatile(InterruptIndex::Keyboard as u8 as u32);
223222
}
224223

225-
226224
fn map_apic(
227225
physical_address: u64,
228226
mapper: &mut impl Mapper<Size4KiB>,
@@ -259,6 +257,8 @@ fn disable_pic() {
259257
pub fn end_interrupt() {
260258
unsafe {
261259
let lapic_ptr = LAPIC_ADDR.lock().address;
262-
lapic_ptr.offset(APICOffset::Eoi as isize / 4).write_volatile(0);
260+
lapic_ptr
261+
.offset(APICOffset::Eoi as isize / 4)
262+
.write_volatile(0);
263263
}
264264
}

‎docs/apic_example/src/frame_allocator.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ impl BootInfoFrameAllocator {
1616
next: 0,
1717
}
1818
}
19-
pub fn usable_frames(&self) -> impl Iterator<Item=PhysFrame> {
19+
pub fn usable_frames(&self) -> impl Iterator<Item = PhysFrame> {
2020
let regions = self.memory_map.iter();
2121

2222
let usable_regions = regions.filter(|region| region.kind == Usable);
@@ -49,4 +49,3 @@ fn active_level4_table(physical_memory_offset: VirtAddr) -> &'static mut PageTab
4949

5050
unsafe { &mut *page_table_pointer }
5151
}
52-

‎docs/apic_example/src/idt.rs

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -45,15 +45,21 @@ pub extern "x86-interrupt" fn handle_breakpoint(stack_frame: InterruptStackFrame
4545
info!("Breakpoint hit:\n{:#?}", stack_frame);
4646
}
4747

48-
pub extern "x86-interrupt" fn handle_double_fault(stack_frame: InterruptStackFrame, _error_code: u64) -> ! {
48+
pub extern "x86-interrupt" fn handle_double_fault(
49+
stack_frame: InterruptStackFrame,
50+
_error_code: u64,
51+
) -> ! {
4952
info!("\nDouble fault:\n{:#?}", stack_frame);
5053

5154
loop {
5255
hlt()
5356
}
5457
}
5558

56-
pub extern "x86-interrupt" fn handle_page_fault(stack_frame: InterruptStackFrame, error_code: PageFaultErrorCode) {
59+
pub extern "x86-interrupt" fn handle_page_fault(
60+
stack_frame: InterruptStackFrame,
61+
error_code: PageFaultErrorCode,
62+
) {
5763
info!("Exception : Page Fault");
5864
info!("Accessed address : {:?}", Cr2::read());
5965
info!("ErrorCode : {:?}", error_code);
@@ -69,5 +75,3 @@ pub extern "x86-interrupt" fn handle_keyboard(_stack_frame: InterruptStackFrame)
6975

7076
apic::end_interrupt();
7177
}
72-
73-

‎docs/apic_example/src/main.rs

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3,15 +3,15 @@
33
#![no_main]
44

55
extern crate alloc;
6-
mod frame_allocator;
76
mod apic;
8-
mod idt;
7+
mod frame_allocator;
98
mod gdt;
9+
mod idt;
1010

11-
use x86_64::instructions::hlt;
1211
use crate::frame_allocator::BootInfoFrameAllocator;
1312
use bootloader_api::config::Mapping;
1413
use bootloader_api::{entry_point, BootInfo};
14+
use x86_64::instructions::hlt;
1515
use x86_64::structures::paging::OffsetPageTable;
1616
use x86_64::VirtAddr;
1717

@@ -37,10 +37,15 @@ pub fn kernel_main(boot_info: &'static mut BootInfo) -> ! {
3737

3838
gdt::init();
3939
unsafe {
40-
apic::init(rsdp.expect("Failed to get RSDP address") as usize, physical_memory_offset, &mut mapper, &mut frame_allocator);
40+
apic::init(
41+
rsdp.expect("Failed to get RSDP address") as usize,
42+
physical_memory_offset,
43+
&mut mapper,
44+
&mut frame_allocator,
45+
);
4146
}
4247

4348
loop {
4449
hlt()
4550
}
46-
}
51+
}

0 commit comments

Comments
 (0)