Sending WIP - squash later

tmvkrpxl0 · tmvkrpxl0 · commit 0bfd3c0912ca · 2025-06-21T20:23:53.000+09:00
diff --git a/uefi-test-runner/src/proto/pci/root_bridge.rs b/uefi-test-runner/src/proto/pci/root_bridge.rs
@@ -1,13 +1,14 @@
 // SPDX-License-Identifier: MIT OR Apache-2.0
 
 use core::mem;
+use qcell::{QCell, QCellOwner};
 use uefi::Handle;
 use uefi::boot::{OpenProtocolAttributes, OpenProtocolParams, ScopedProtocol, image_handle};
 use uefi::proto::ProtocolPointer;
 use uefi::proto::pci::PciIoAddress;
 use uefi::proto::pci::root_bridge::PciRootBridgeIo;
-use uefi_raw::protocol::pci::root_bridge::{PciRootBridgeIoProtocolAttribute, PciRootBridgeIoProtocolOperation};
-use uefi_raw::table::boot::MemoryType;
+use uefi_raw::protocol::pci::root_bridge::{PciRootBridgeIoProtocolAttribute, PciRootBridgeIoProtocolOperation, PciRootBridgeIoProtocolWidth};
+use uefi_raw::table::boot::{MemoryType, PAGE_SIZE};
 
 const RED_HAT_PCI_VENDOR_ID: u16 = 0x1AF4;
 const MASS_STORAGE_CTRL_CLASS_CODE: u8 = 0x1;
@@ -108,14 +109,54 @@ pub fn test_mapping() {
             buffer.assume_init()
         };
         let mapped = pci_proto.map(PciRootBridgeIoProtocolOperation::BUS_MASTER_COMMON_BUFFER64, buffer.as_ref());
-        if mapped.region().0 == buffer.as_ptr().addr() as u64 {
+        if mapped.region().device_address == buffer.as_ptr().addr() as u64 {
             info!("This PCI device uses identity mapping");
         } else {
             info!("This PCI device uses different mapping from CPU");
         }
     }
 }
 
+pub fn test_copy() {
+    let pci_handles = uefi::boot::find_handles::<PciRootBridgeIo>().unwrap();
+
+    for pci_handle in pci_handles {
+        let mut owner = QCellOwner::new();
+        let item = QCell::new(&owner, get_open_protocol::<PciRootBridgeIo>(pci_handle));
+        let pci_proto = owner.rw(&item);
+
+        let mut src = pci_proto
+            .allocate_buffer::<[u32; 4096 / 4]>(
+                MemoryType::BOOT_SERVICES_DATA,
+                None,
+                PciRootBridgeIoProtocolAttribute::PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
+            )
+            .unwrap();
+        assert_eq!(size_of_val(src.as_ref()), size_of::<[u8; PAGE_SIZE]>());
+        let src = unsafe {
+            src.assume_init_mut().fill(0xDEADBEEF);
+            src.assume_init()
+        };
+        let src_mapped = pci_proto.map(PciRootBridgeIoProtocolOperation::BUS_MASTER_READ, src.as_ref());
+
+        let dst = pci_proto
+            .allocate_buffer::<[u32; 4096 / 4]>(
+                MemoryType::BOOT_SERVICES_DATA,
+                None,
+                PciRootBridgeIoProtocolAttribute::PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
+            )
+            .unwrap();
+        assert_eq!(size_of_val(dst.as_ref()), size_of::<[u8; PAGE_SIZE]>());
+        let dst_mapped = pci_proto.map(PciRootBridgeIoProtocolOperation::BUS_MASTER_WRITE, dst.as_ref());
+
+        pci_proto.copy(PciRootBridgeIoProtocolWidth::UINT32, dst_mapped.region(), src_mapped.region()).unwrap();
+        drop(dst_mapped);
+        let dst = unsafe { dst.assume_init() };
+
+        assert!(dst.iter().all(|&b| b == 0xDEADBEEF));
+    }
+}
+
 fn get_open_protocol<P: ProtocolPointer + ?Sized>(handle: Handle) -> ScopedProtocol<P> {
     let open_opts = OpenProtocolParams {
         handle,
diff --git a/uefi/src/proto/pci/buffer.rs b/uefi/src/proto/pci/buffer.rs
@@ -5,6 +5,7 @@
 use core::mem::{ManuallyDrop, MaybeUninit};
 use core::num::NonZeroUsize;
 use core::ops::{Deref, DerefMut};
+use core::ptr;
 use core::ptr::NonNull;
 use log::debug;
 use uefi_raw::Status;
@@ -13,12 +14,27 @@ use uefi_raw::protocol::pci::root_bridge::PciRootBridgeIoProtocol;
 /// Smart pointer for wrapping owned buffer allocated by PCI Root Bridge protocol.
 #[derive(Debug)]
 pub struct PciBuffer<'p, T> {
-    pub(crate) base: NonNull<T>,
-    pub(crate) pages: NonZeroUsize,
-    pub(crate) proto: &'p PciRootBridgeIoProtocol,
+    base: NonNull<T>,
+    pages: NonZeroUsize,
+    proto_lifetime: &'p (),
+    proto: *const PciRootBridgeIoProtocol,
 }
 
 impl<'p, T> PciBuffer<'p, MaybeUninit<T>> {
+
+    /// Creates wrapper for buffer allocated by PCI Root Bridge protocol.
+    /// Passed protocol is stored as a pointer along with its lifetime so that it doesn't
+    /// block others from using its mutable functions.
+    #[must_use]
+    pub const fn new(base: NonNull<MaybeUninit<T>>, pages: NonZeroUsize, proto: &'p PciRootBridgeIoProtocol) -> Self {
+        Self {
+            base,
+            pages,
+            proto_lifetime: &(),
+            proto: ptr::from_ref(proto),
+        }
+    }
+
     /// Assumes the contents of this buffer have been initialized.
     ///
     /// # Safety
@@ -29,6 +45,7 @@ impl<'p, T> PciBuffer<'p, MaybeUninit<T>> {
         PciBuffer {
             base: old.base.cast(),
             pages: old.pages,
+            proto_lifetime: old.proto_lifetime,
             proto: old.proto,
         }
     }
@@ -63,7 +80,8 @@ impl<'p, T> DerefMut for PciBuffer<'p, T> {
 impl<'p, T> Drop for PciBuffer<'p, T> {
     fn drop(&mut self) {
         let status = unsafe {
-            (self.proto.free_buffer)(self.proto, self.pages.get(), self.base.as_ptr().cast())
+            let proto = self.proto.as_ref().unwrap();
+            (proto.free_buffer)(proto, self.pages.get(), self.base.as_ptr().cast())
         };
         match status {
             Status::SUCCESS => {
diff --git a/uefi/src/proto/pci/mod.rs b/uefi/src/proto/pci/mod.rs
@@ -7,7 +7,7 @@ use core::cmp::Ordering;
 use uefi_raw::protocol::pci::root_bridge::PciRootBridgeIoProtocolWidth;
 
 pub mod buffer;
-pub mod mapped_region;
+pub mod region;
 pub mod root_bridge;
 
 /// IO Address for PCI/register IO operations
diff --git a/uefi/src/proto/pci/region.rs b/uefi/src/proto/pci/region.rs
@@ -21,13 +21,25 @@ pub struct PciMappedRegion<'p, 'r>
 where
     'p: 'r,
 {
-    device_address: u64,
-    length: usize,
+    region: PciRegion,
     _lifetime_holder: &'r (),
     key: *const c_void,
     proto: &'p PciRootBridgeIoProtocol,
 }
 
+/// Represents a region of memory in PCI root bridge memory space.
+/// CPU cannot use address in this struct to deference memory.
+/// This is effectively the same as rust's slice type.
+/// This type only exists to prevent users from accidentally dereferencing it.
+#[derive(Debug, Copy, Clone)]
+pub struct PciRegion {
+    /// Starting address of the memory region
+    pub device_address: u64,
+
+    /// Byte length of the memory region.
+    pub length: usize
+}
+
 impl<'p, 'r> PciMappedRegion<'p, 'r> where 'p: 'r {
     pub(crate) fn new<T>(
         device_address: u64,
@@ -44,8 +56,10 @@ impl<'p, 'r> PciMappedRegion<'p, 'r> where 'p: 'r {
         let end = device_address + length as u64;
         debug!("Mapped new region [0x{:X}..0x{:X}]", device_address, end);
         Self {
-            device_address,
-            length,
+            region: PciRegion {
+                device_address,
+                length,
+            },
             _lifetime_holder,
             key,
             proto,
@@ -58,8 +72,8 @@ impl<'p, 'r> PciMappedRegion<'p, 'r> where 'p: 'r {
     /// **Returned address cannot be used to reference memory from CPU!**
     /// **Do not cast it back to pointer or reference**
     #[must_use]
-    pub const fn region(&self) -> (u64, usize) {
-        (self.device_address, self.length)
+    pub const fn region(&self) -> PciRegion {
+        self.region
     }
 }
 
@@ -68,8 +82,8 @@ impl<'p, 'r> Drop for PciMappedRegion<'p, 'r> {
         let status = unsafe { (self.proto.unmap)(self.proto, self.key) };
         match status {
             Status::SUCCESS => {
-                let end = self.device_address + self.length as u64;
-                debug!("Region [0x{:X}..0x{:X}] was unmapped", self.device_address, end);
+                let end = self.region.device_address + self.region.length as u64;
+                debug!("Region [0x{:X}..0x{:X}] was unmapped", self.region.device_address, end);
             }
             Status::INVALID_PARAMETER => {
                 panic!("This region was not mapped using PciRootBridgeIo::map");
@@ -81,3 +95,17 @@ impl<'p, 'r> Drop for PciMappedRegion<'p, 'r> {
         }
     }
 }
+
+impl PciRegion {
+    /// Creates a new region of memory with different length.
+    /// The new region must have shorter length to ensure
+    /// it won't contain invalid memory address.
+    #[must_use]
+    pub fn with_length(self, new_length: usize) -> Self {
+        assert!(new_length <= self.length);
+        Self {
+            device_address: self.device_address,
+            length: new_length,
+        }
+    }
+}
diff --git a/uefi/src/proto/pci/root_bridge.rs b/uefi/src/proto/pci/root_bridge.rs
@@ -5,7 +5,7 @@
 use super::{PciIoAddress, PciIoUnit, encode_io_mode_and_unit};
 use crate::StatusExt;
 use crate::proto::pci::buffer::PciBuffer;
-use crate::proto::pci::mapped_region::PciMappedRegion;
+use crate::proto::pci::region::{PciMappedRegion, PciRegion};
 use core::ffi::c_void;
 use core::mem::MaybeUninit;
 use core::num::NonZeroUsize;
@@ -14,10 +14,7 @@ use core::ptr::NonNull;
 use log::debug;
 use uefi_macros::unsafe_protocol;
 use uefi_raw::Status;
-use uefi_raw::protocol::pci::root_bridge::{
-    PciRootBridgeIoAccess, PciRootBridgeIoProtocol, PciRootBridgeIoProtocolAttribute,
-    PciRootBridgeIoProtocolOperation,
-};
+use uefi_raw::protocol::pci::root_bridge::{PciRootBridgeIoAccess, PciRootBridgeIoProtocol, PciRootBridgeIoProtocolAttribute, PciRootBridgeIoProtocolOperation, PciRootBridgeIoProtocolWidth};
 use uefi_raw::table::boot::{AllocateType, MemoryType, PAGE_SIZE};
 
 /// Protocol that provides access to the PCI Root Bridge I/O protocol.
@@ -48,7 +45,7 @@ impl PciRootBridgeIo {
     /// Flush all PCI posted write transactions from a PCI host bridge to system memory.
     ///
     /// # Errors
-    /// - [`crate::Status::DEVICE_ERROR`] The PCI posted write transactions were not flushed from the PCI host bridge
+    /// - [`Status::DEVICE_ERROR`] The PCI posted write transactions were not flushed from the PCI host bridge
     ///   due to a hardware error.
     pub fn flush(&mut self) -> crate::Result<()> {
         unsafe { (self.0.flush)(&mut self.0).to_result() }
@@ -57,12 +54,12 @@ impl PciRootBridgeIo {
     /// Allocates pages suitable for communicating with PCI devices.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] MemoryType is invalid.
-    /// - [`crate::Status::UNSUPPORTED`] Attributes is unsupported. The only legal attribute bits are:
+    /// - [`Status::INVALID_PARAMETER`] MemoryType is invalid.
+    /// - [`Status::UNSUPPORTED`] Attributes is unsupported. The only legal attribute bits are:
     ///   - [`PciRootBridgeIoProtocolAttribute::PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE`]
     ///   - [`PciRootBridgeIoProtocolAttribute::PCI_ATTRIBUTE_MEMORY_CACHED`]
     ///   - [`PciRootBridgeIoProtocolAttribute::PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE`]
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The memory pages could not be allocated.
+    /// - [`Status::OUT_OF_RESOURCES`] The memory pages could not be allocated.
     pub fn allocate_buffer<T>(
         &self,
         memory_type: MemoryType,
@@ -101,11 +98,7 @@ impl PciRootBridgeIo {
             Status::SUCCESS => {
                 let base = NonNull::new(address as *mut MaybeUninit<T>).unwrap();
                 debug!("Allocated {} pages at 0x{:X}", pages.get(), address);
-                Ok(PciBuffer {
-                    base,
-                    pages,
-                    proto: &self.0,
-                })
+                Ok(PciBuffer::new(base, pages, &self.0))
             }
             error
             @ (Status::INVALID_PARAMETER | Status::UNSUPPORTED | Status::OUT_OF_RESOURCES) => {
@@ -155,10 +148,37 @@ impl PciRootBridgeIo {
         }
     }
 
+    /// Copies a region in PCI root bridge memory space onto the other.
+    /// Two regions must have same length. Functionally, this is the same as
+    /// `<[T]>::copy_from_slice` which is effectively memcpy.
+    /// And the same safety requirements as the above method apply.
+    pub fn copy(
+        &mut self,
+        width: PciRootBridgeIoProtocolWidth,
+        destination: PciRegion,
+        source: PciRegion,
+    ) -> crate::Result<()> {
+        assert_eq!(destination.length, source.length);
+
+        let status = unsafe {
+            (self.0.copy_mem)(
+                &mut self.0,
+                width,
+                destination.device_address,
+                source.device_address,
+                destination.length,
+            )
+        };
+
+        match status {
+            Status::SUCCESS => Ok(()),
+            error => Err(error.into()),
+        }
+    }
+
     // TODO: poll I/O
     // TODO: mem I/O access
     // TODO: io I/O access
-    // TODO: copy memory
     // TODO: get/set attributes
     // TODO: configuration / resource settings
 }
@@ -180,8 +200,8 @@ impl PciIoAccessPci<'_> {
     /// - The read value of type `U`.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The read request could not be completed due to a lack of resources.
+    /// - [`Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
+    /// - [`Status::OUT_OF_RESOURCES`] The read request could not be completed due to a lack of resources.
     pub fn read_one<U: PciIoUnit>(&self, addr: PciIoAddress) -> crate::Result<U> {
         let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
         let mut result = U::default();
@@ -204,8 +224,8 @@ impl PciIoAccessPci<'_> {
     /// - `data` - The value to write.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The write request could not be completed due to a lack of resources.
+    /// - [`Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
+    /// - [`Status::OUT_OF_RESOURCES`] The write request could not be completed due to a lack of resources.
     pub fn write_one<U: PciIoUnit>(&self, addr: PciIoAddress, data: U) -> crate::Result<()> {
         let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
         unsafe {
@@ -227,8 +247,8 @@ impl PciIoAccessPci<'_> {
     /// - `data` - A mutable slice to store the read values.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The read operation could not be completed due to a lack of resources.
+    /// - [`Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
+    /// - [`Status::OUT_OF_RESOURCES`] The read operation could not be completed due to a lack of resources.
     pub fn read<U: PciIoUnit>(&self, addr: PciIoAddress, data: &mut [U]) -> crate::Result<()> {
         let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
         unsafe {
@@ -250,8 +270,8 @@ impl PciIoAccessPci<'_> {
     /// - `data` - A slice containing the values to write.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The write operation could not be completed due to a lack of resources.
+    /// - [`Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
+    /// - [`Status::OUT_OF_RESOURCES`] The write operation could not be completed due to a lack of resources.
     pub fn write<U: PciIoUnit>(&self, addr: PciIoAddress, data: &[U]) -> crate::Result<()> {
         let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
         unsafe {
@@ -274,8 +294,8 @@ impl PciIoAccessPci<'_> {
     /// - `data` - The value to fill the address range with.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The operation could not be completed due to a lack of resources.
+    /// - [`Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
+    /// - [`Status::OUT_OF_RESOURCES`] The operation could not be completed due to a lack of resources.
     pub fn fill_write<U: PciIoUnit>(
         &self,
         addr: PciIoAddress,
@@ -306,8 +326,8 @@ impl PciIoAccessPci<'_> {
     /// The resulting `data` buffer will contain the elements returned by reading the same address multiple times sequentially.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The read operation could not be completed due to a lack of resources.
+    /// - [`Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
+    /// - [`Status::OUT_OF_RESOURCES`] The read operation could not be completed due to a lack of resources.
     pub fn fifo_read<U: PciIoUnit>(&self, addr: PciIoAddress, data: &mut [U]) -> crate::Result<()> {
         let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Fifo);
         unsafe {
@@ -333,8 +353,8 @@ impl PciIoAccessPci<'_> {
     /// (starting at `addr` and ending at `addr + size_of::<U>()`) sequentially.
     ///
     /// # Errors
-    /// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
-    /// - [`crate::Status::OUT_OF_RESOURCES`] The write operation could not be completed due to a lack of resources.
+    /// - [`Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
+    /// - [`Status::OUT_OF_RESOURCES`] The write operation could not be completed due to a lack of resources.
     pub fn fifo_write<U: PciIoUnit>(&self, addr: PciIoAddress, data: &[U]) -> crate::Result<()> {
         let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Fifo);
         unsafe {
