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Merge pull request #1732 from PelleKrab/uefi_raw_IoMmu
feat: `uefi-raw` IoMmu Protocol Impl
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uefi-raw/src/protocol/iommu.rs

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// SPDX-License-Identifier: MIT OR Apache-2.0
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use crate::table::boot::{AllocateType, MemoryType};
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use crate::{Guid, Handle, Status, guid};
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use bitflags::bitflags;
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use core::ffi::c_void;
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use crate::newtype_enum;
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/// EDKII IOMMU Protocol GUID
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impl EdkiiIommuProtocol {
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pub const GUID: Guid = guid!("4e939de9-d948-4b0f-88ed-e6e1ce517c1e");
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}
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#[derive(Debug)]
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#[repr(C)]
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pub struct EdkiiIommuProtocol {
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pub revision: u64,
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pub set_attribute: unsafe extern "efiapi" fn(
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this: *const Self,
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device_handle: Handle,
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mapping: *mut c_void,
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iommu_access: EdkiiIommuAccess,
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) -> Status,
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pub map: unsafe extern "efiapi" fn(
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this: *const Self,
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operation: EdkiiIommuOperation,
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host_address: *mut c_void,
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number_of_bytes: *mut usize,
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device_address: *mut u64,
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mapping: *mut *mut c_void,
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) -> Status,
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pub unmap: unsafe extern "efiapi" fn(this: *const Self, mapping: *mut c_void) -> Status,
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pub allocate_buffer: unsafe extern "efiapi" fn(
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this: *const Self,
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allocate_type: AllocateType,
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memory_type: MemoryType,
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pages: usize,
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host_address: *mut *mut c_void,
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attributes: EdkiiIommuAttribute,
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) -> Status,
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pub free_buffer: unsafe extern "efiapi" fn(
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this: *const Self,
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pages: usize,
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host_address: *mut c_void,
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) -> Status,
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}
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newtype_enum! {
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/// IOMMU Operation for Map (matches EDKII_IOMMU_OPERATION)
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pub enum EdkiiIommuOperation: u32 => {
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/// A read operation from system memory by a bus master that is not capable of producing PCI dual address cycles.
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BUS_MASTER_READ = 0,
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/// A write operation to system memory by a bus master that is not capable of producing PCI dual address cycles.
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BUS_MASTER_WRITE = 1,
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/// Provides both read and write access to system memory by both the processor and a bus master that is not capable of producing PCI dual address cycles.
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BUS_MASTER_COMMON_BUFFER = 2,
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/// A read operation from system memory by a bus master that is capable of producing PCI dual address cycles.
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BUS_MASTER_READ64 = 3,
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/// A write operation to system memory by a bus master that is capable of producing PCI dual address cycles.
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BUS_MASTER_WRITE64 = 4,
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/// Provides both read and write access to system memory by both the processor and a bus master that is capable of producing PCI dual address cycles.
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BUS_MASTER_COMMON_BUFFER64 = 5,
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/// Maximum value (not a valid operation, for bounds checking)
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MAXIMUM = 6,
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}
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}
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/// EDKII IOMMU protocol revision constant
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pub const EDKII_IOMMU_PROTOCOL_REVISION: u64 = 0x0001_0000;
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bitflags! {
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/// EDKII IOMMU attribute flags
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#[repr(transparent)]
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
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pub struct EdkiiIommuAttribute: u64 {
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/// Memory is write-combined
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const MEMORY_WRITE_COMBINE = 0x0080;
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/// Memory is cached
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const MEMORY_CACHED = 0x0800;
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/// Dual address cycle supported
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const DUAL_ADDRESS_CYCLE = 0x8000;
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}
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}
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impl EdkiiIommuAttribute {
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/// Valid attributes for allocate_buffer
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pub const VALID_FOR_ALLOCATE_BUFFER: Self = Self::from_bits_truncate(
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Self::MEMORY_WRITE_COMBINE.bits()
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| Self::MEMORY_CACHED.bits()
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| Self::DUAL_ADDRESS_CYCLE.bits(),
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);
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/// Invalid attributes for allocate_buffer (all bits except valid)
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pub const INVALID_FOR_ALLOCATE_BUFFER: Self =
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Self::from_bits_truncate(!Self::VALID_FOR_ALLOCATE_BUFFER.bits());
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}
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bitflags! {
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/// EDKII IOMMU access flags for SetAttribute
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#[repr(transparent)]
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
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pub struct EdkiiIommuAccess: u64 {
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/// Read access
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const READ = 0x1;
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/// Write access
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const WRITE = 0x2;
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}
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}

uefi-raw/src/protocol/mod.rs

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pub mod file_system;
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pub mod firmware_volume;
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pub mod hii;
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pub mod iommu;
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pub mod loaded_image;
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pub mod media;
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pub mod memory_protection;

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