add PageFaultErrorCode::HLAT

Some Intel CPUs have a feature called hypervisor-managed linear-address
translation (HLAT). The details of how HLAT paging works are a bit to
complicated for this commit message, but suffice it to say that with
HLAT, there are two root page tables, the regular PML4/PML5 and the
HLAT pointer (HLATP). If the page fault occured while translating with
the HLATP, the HLAT bit (7) is set in the error code. If the page fault
occured while translating with the regular PML4/PML5, the HLAT bit is
not set.

Author: Freax13

src/structures/idt.rs

@@ -1198,6 +1198,10 @@ bitflags! {
         /// access.
         const SHADOW_STACK = 1 << 6;
 
+        /// If this flag is set, it indicates that the page fault occured during HLAT paging
+        /// (Intel-only).
+        const HLAT = 1 << 7;
+
         /// If this flag is set, it indicates that the page fault was caused by SGX access-control
         /// requirements (Intel-only).
         const SGX = 1 << 15;