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| 1 | +// Copyright © 2024 Institute of Software, CAS. All rights reserved. |
| 2 | +// |
1 | 3 | // Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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2 | 4 | // SPDX-License-Identifier: Apache-2.0 OR MIT
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3 | 5 | //
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21 | 23 | //!
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22 | 24 | //! - x86_64
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23 | 25 | //! - arm64 (experimental)
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| 26 | +//! - riscv64 (experimental) |
24 | 27 | //!
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25 | 28 | //! **NOTE:** The list of available ioctls is not extensive.
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26 | 29 | //!
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30 | 33 | //! On the vCPU we are running machine specific code. This example is based on
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31 | 34 | //! the [LWN article](https://lwn.net/Articles/658511/) on using the KVM API.
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32 | 35 | //! The aarch64 example was modified accordingly.
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| 36 | +//! The riscv64 example was modified accordingly. |
33 | 37 | //!
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34 | 38 | //! To get code running on the vCPU we are going through the following steps:
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35 | 39 | //!
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93 | 97 | //! 0x14, /* b <this address>; shouldn't get here, but if so loop forever */
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94 | 98 | //! ];
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95 | 99 | //! }
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| 100 | +//! #[cfg(target_arch = "riscv64")] |
| 101 | +//! { |
| 102 | +//! asm_code = &[ |
| 103 | +//! 0x17, 0x03, 0x00, 0x00, // auipc t1, 0; <this address> -> t1 |
| 104 | +//! 0xa3, 0x23, 0x73, 0x00, // sw t2, t1 + 7; dirty current page |
| 105 | +//! 0x23, 0x20, 0x75, 0x00, // sw t2, a0; trigger MMIO exit |
| 106 | +//! 0x6f, 0x00, 0x00, 0x00, // j .;shouldn't get here, but if so loop forever |
| 107 | +//! ]; |
| 108 | +//! } |
96 | 109 | //!
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97 | 110 | //! // 1. Instantiate KVM.
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98 | 111 | //! let kvm = Kvm::new().unwrap();
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165 | 178 | //! vcpu_fd.set_one_reg(core_reg_base + 2 * 0, &mmio_addr.to_le_bytes());
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166 | 179 | //! }
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167 | 180 | //!
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| 181 | +//! #[cfg(target_arch = "riscv64")] |
| 182 | +//! { |
| 183 | +//! // riscv64 specific register setup. |
| 184 | +//! let core_reg_base: u64 = 0x8030_0000_0200_0000; |
| 185 | +//! let mmio_addr: u64 = guest_addr + mem_size as u64; |
| 186 | +//! // set PC |
| 187 | +//! vcpu_fd.set_one_reg(core_reg_base, &guest_addr.to_le_bytes()); |
| 188 | +//! // set A0 |
| 189 | +//! vcpu_fd.set_one_reg(core_reg_base + 10, &mmio_addr.to_le_bytes()); |
| 190 | +//! } |
| 191 | +//! |
168 | 192 | //! // 6. Run code on the vCPU.
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169 | 193 | //! loop {
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170 | 194 | //! match vcpu_fd.run().expect("run failed") {
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195 | 219 | //! // Since on aarch64 there is not halt instruction,
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196 | 220 | //! // we break immediately after the last known instruction
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197 | 221 | //! // of the asm code example so that we avoid an infinite loop.
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198 |
| -//! #[cfg(target_arch = "aarch64")] |
| 222 | +//! #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] |
199 | 223 | //! break;
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200 | 224 | //! }
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201 | 225 | //! VcpuExit::Hlt => {
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