riscv64: add bindings for sbi ecall interface

Generate bindings from qemu-10.1.0  target\riscv\sbi_ecall_interface.h
using bindgen-cli 0.72.1

Signed-off-by: BillXiang <[email protected]>

Author: BillXiang

kvm-bindings/src/riscv64/mod.rs

@@ -5,12 +5,14 @@
 #[allow(clippy::all)]
 #[allow(clippy::undocumented_unsafe_blocks)]
 pub mod bindings;
+pub mod sbi_bindings;
 #[cfg(feature = "fam-wrappers")]
 pub mod fam_wrappers;
 
 #[cfg(feature = "serde")]
 mod serialize;
 
 pub use self::bindings::*;
+pub use self::sbi_bindings::*;
 #[cfg(feature = "fam-wrappers")]
 pub use self::fam_wrappers::*;

kvm-bindings/src/riscv64/sbi_bindings.rs

@@ -0,0 +1,58 @@
+/* automatically generated by rust-bindgen 0.72.1 */
+
+pub const SBI_SUCCESS: u32 = 0;
+pub const SBI_ERR_FAILED: i32 = -1;
+pub const SBI_ERR_NOT_SUPPORTED: i32 = -2;
+pub const SBI_ERR_INVALID_PARAM: i32 = -3;
+pub const SBI_ERR_DENIED: i32 = -4;
+pub const SBI_ERR_INVALID_ADDRESS: i32 = -5;
+pub const SBI_ERR_ALREADY_AVAILABLE: i32 = -6;
+pub const SBI_ERR_ALREADY_STARTED: i32 = -7;
+pub const SBI_ERR_ALREADY_STOPPED: i32 = -8;
+pub const SBI_ERR_NO_SHMEM: i32 = -9;
+pub const SBI_EXT_0_1_SET_TIMER: u32 = 0;
+pub const SBI_EXT_0_1_CONSOLE_PUTCHAR: u32 = 1;
+pub const SBI_EXT_0_1_CONSOLE_GETCHAR: u32 = 2;
+pub const SBI_EXT_0_1_CLEAR_IPI: u32 = 3;
+pub const SBI_EXT_0_1_SEND_IPI: u32 = 4;
+pub const SBI_EXT_0_1_REMOTE_FENCE_I: u32 = 5;
+pub const SBI_EXT_0_1_REMOTE_SFENCE_VMA: u32 = 6;
+pub const SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID: u32 = 7;
+pub const SBI_EXT_0_1_SHUTDOWN: u32 = 8;
+pub const SBI_EXT_BASE: u32 = 16;
+pub const SBI_EXT_TIME: u32 = 1414090053;
+pub const SBI_EXT_IPI: u32 = 7557193;
+pub const SBI_EXT_RFENCE: u32 = 1380339267;
+pub const SBI_EXT_HSM: u32 = 4739917;
+pub const SBI_EXT_DBCN: u32 = 1145193294;
+pub const SBI_EXT_BASE_GET_SPEC_VERSION: u32 = 0;
+pub const SBI_EXT_BASE_GET_IMP_ID: u32 = 1;
+pub const SBI_EXT_BASE_GET_IMP_VERSION: u32 = 2;
+pub const SBI_EXT_BASE_PROBE_EXT: u32 = 3;
+pub const SBI_EXT_BASE_GET_MVENDORID: u32 = 4;
+pub const SBI_EXT_BASE_GET_MARCHID: u32 = 5;
+pub const SBI_EXT_BASE_GET_MIMPID: u32 = 6;
+pub const SBI_EXT_TIME_SET_TIMER: u32 = 0;
+pub const SBI_EXT_IPI_SEND_IPI: u32 = 0;
+pub const SBI_EXT_RFENCE_REMOTE_FENCE_I: u32 = 0;
+pub const SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: u32 = 1;
+pub const SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: u32 = 2;
+pub const SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: u32 = 3;
+pub const SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: u32 = 4;
+pub const SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA: u32 = 5;
+pub const SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID: u32 = 6;
+pub const SBI_EXT_HSM_HART_START: u32 = 0;
+pub const SBI_EXT_HSM_HART_STOP: u32 = 1;
+pub const SBI_EXT_HSM_HART_GET_STATUS: u32 = 2;
+pub const SBI_EXT_DBCN_CONSOLE_WRITE: u32 = 0;
+pub const SBI_EXT_DBCN_CONSOLE_READ: u32 = 1;
+pub const SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: u32 = 2;
+pub const SBI_HSM_HART_STATUS_STARTED: u32 = 0;
+pub const SBI_HSM_HART_STATUS_STOPPED: u32 = 1;
+pub const SBI_HSM_HART_STATUS_START_PENDING: u32 = 2;
+pub const SBI_HSM_HART_STATUS_STOP_PENDING: u32 = 3;
+pub const SBI_SPEC_VERSION_MAJOR_OFFSET: u32 = 24;
+pub const SBI_SPEC_VERSION_MAJOR_MASK: u32 = 127;
+pub const SBI_SPEC_VERSION_MINOR_MASK: u32 = 16777215;
+pub const SBI_EXT_VENDOR_START: u32 = 150994944;
+pub const SBI_EXT_VENDOR_END: u32 = 167772159;