feat(allwinner-hal): add ledc ccu

feat(examples): add nezha-d1-blinky

Signed-off-by: Woshiluo Luo <woshiluo.luo@outlook.com>

Author: woshiluo

allwinner-hal/src/ccu.rs

@@ -308,3 +308,48 @@ impl<const I: usize> ClockConfig for SPI<I> {
         }
     }
 }
+
+/// LED Control (LEDC) clock type.
+pub struct LEDC;
+
+impl ClockReset for LEDC {
+    #[inline]
+    unsafe fn deassert_reset_only(ccu: &RegisterBlock) {
+        unsafe {
+            ccu.ledc_bgr.modify(|v| v.deassert_reset());
+        }
+    }
+    #[inline]
+    unsafe fn assert_reset_only(ccu: &RegisterBlock) {
+        unsafe {
+            ccu.ledc_bgr.modify(|v| v.assert_reset());
+        }
+    }
+}
+
+impl ClockGate for LEDC {
+    #[inline]
+    unsafe fn unmask_gate_only(ccu: &RegisterBlock) {
+        unsafe {
+            ccu.ledc_bgr.modify(|v| v.gate_pass());
+        }
+    }
+    #[inline]
+    unsafe fn mask_gate_only(ccu: &RegisterBlock) {
+        unsafe {
+            ccu.ledc_bgr.modify(|v| v.gate_mask());
+        }
+    }
+    #[inline]
+    unsafe fn disable_in(ccu: &RegisterBlock) {
+        unsafe {
+            ccu.ledc_bgr.modify(|v| v.gate_mask().assert_reset());
+        }
+    }
+    #[inline]
+    unsafe fn enable_in(ccu: &RegisterBlock) {
+        unsafe {
+            ccu.ledc_bgr.modify(|v| v.gate_pass().deassert_reset());
+        }
+    }
+}

allwinner-hal/src/ccu/register.rs

@@ -44,6 +44,12 @@ pub struct RegisterBlock {
     _reserved10: [u32; 9],
     /// 0x96c - SPI Bus Gating Reset register.
     pub spi_bgr: RW<SpiBusGating>,
+    _reserved11: [u32; 0xA0],
+    /// 0xbf0 - LDEC Clock register.
+    pub ledc_clk: RW<LedcClock>,
+    _reserved12: [u32; 2],
+    /// 0xbfc - LDEC Bus Gating Reset register.
+    pub ledc_bgr: RW<LedcBusGating>,
 }
 
 /// CPU AXI Configuration register.
@@ -493,6 +499,113 @@ impl SmhcBusGating {
     }
 }
 
+/// LEDC Clock register.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
+#[repr(transparent)]
+pub struct LedcClock(u32);
+
+impl LedcClock {
+    const CLK_SRC_SEL: u32 = 1 << 24;
+    const FACTOR_N: u32 = 0x3 << 8;
+    const FACTOR_M: u32 = 0xf << 0;
+    const CLK_GATING: u32 = 1 << 31;
+
+    /// Get LEDC clock source.
+    #[inline]
+    pub const fn clock_source(self) -> SmhcClockSource {
+        match (self.0 & Self::CLK_SRC_SEL) >> 24 {
+            0x0 => SmhcClockSource::Hosc,
+            0x1 => SmhcClockSource::PllPeri1x,
+            _ => panic!("impossible clock source"),
+        }
+    }
+    /// Set LEDC clock source.
+    #[inline]
+    pub const fn set_clock_source(self, val: SmhcClockSource) -> Self {
+        let val = match val {
+            SmhcClockSource::Hosc => 0x0,
+            SmhcClockSource::PllPeri1x => 0x1,
+            _ => panic!("impossible clock source"),
+        };
+        Self((self.0 & !Self::CLK_SRC_SEL) | (val << 24))
+    }
+    /// Get LEDC clock divide factor N.
+    #[inline]
+    pub const fn factor_n(self) -> PeriFactorN {
+        match (self.0 & Self::FACTOR_N) >> 8 {
+            0 => PeriFactorN::N1,
+            1 => PeriFactorN::N2,
+            2 => PeriFactorN::N4,
+            3 => PeriFactorN::N8,
+            _ => unreachable!(),
+        }
+    }
+    /// Set LEDC clock divide factor N.
+    #[inline]
+    pub const fn set_factor_n(self, val: PeriFactorN) -> Self {
+        let val = match val {
+            PeriFactorN::N1 => 0,
+            PeriFactorN::N2 => 1,
+            PeriFactorN::N4 => 2,
+            PeriFactorN::N8 => 3,
+        };
+        Self((self.0 & !Self::FACTOR_N) | (val << 8))
+    }
+    /// Get LEDC clock divide factor M.
+    #[inline]
+    pub const fn factor_m(self) -> u8 {
+        (self.0 & Self::FACTOR_M) as u8
+    }
+    /// Set LEDC clock divide factor M.
+    #[inline]
+    pub const fn set_factor_m(self, val: u8) -> Self {
+        Self((self.0 & !Self::FACTOR_M) | val as u32)
+    }
+    /// Enable clock gating.
+    #[inline]
+    pub const fn enable_clock_gating(self) -> Self {
+        Self(self.0 | Self::CLK_GATING)
+    }
+    /// Disable clock gating.
+    #[inline]
+    pub const fn disable_clock_gating(self) -> Self {
+        Self(self.0 & !Self::CLK_GATING)
+    }
+    /// Get if clock gating is enabled.
+    #[inline]
+    pub const fn is_clock_gating_enabled(self) -> bool {
+        self.0 & Self::CLK_GATING != 0
+    }
+}
+
+/// LEDC Clock Reset register.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
+#[repr(transparent)]
+pub struct LedcBusGating(u32);
+
+impl LedcBusGating {
+    /// Disable clock gate for LEDC.
+    #[inline]
+    pub const fn gate_mask(self) -> Self {
+        Self(self.0 & !(1 << 0))
+    }
+    /// Enable clock gate for LEDC.
+    #[inline]
+    pub const fn gate_pass(self) -> Self {
+        Self(self.0 | (1 << 0))
+    }
+    /// Assert reset signal for LEDC.
+    #[inline]
+    pub const fn assert_reset(self) -> Self {
+        Self(self.0 & !(1 << (0 + 16)))
+    }
+    /// Deassert reset signal for LEDC.
+    #[inline]
+    pub const fn deassert_reset(self) -> Self {
+        Self(self.0 | (1 << (0 + 16)))
+    }
+}
+
 #[cfg(test)]
 mod tests {
     use super::{
@@ -514,6 +627,8 @@ mod tests {
         assert_eq!(offset_of!(RegisterBlock, uart_bgr), 0x90c);
         assert_eq!(offset_of!(RegisterBlock, spi_clk), 0x940);
         assert_eq!(offset_of!(RegisterBlock, spi_bgr), 0x96c);
+        assert_eq!(offset_of!(RegisterBlock, ledc_clk), 0xbf0);
+        assert_eq!(offset_of!(RegisterBlock, ledc_bgr), 0xbfc);
     }
 
     #[test]

examples/nezha-d1/src/bin/nezha-d1-blinky.rs

@@ -1,10 +1,71 @@
 #![no_std]
 #![no_main]
 
-// use allwinner_hal::prelude::*;
+use allwinner_hal::{ccu::*, prelude::*};
 use allwinner_rt::{Clocks, Peripherals, entry};
 
+#[inline]
+fn sleep(n: u32) {
+    for _ in 0..n * 100_000 {
+        unsafe { core::arch::asm!("nop") }
+    }
+}
+
 #[entry]
 fn main(p: Peripherals, _c: Clocks) {
-    // TODO implement using LEDC peripheral
+    unsafe {
+        LEDC::unmask_gate_only(&p.ccu);
+        LEDC::enable_in(&p.ccu);
+        p.ccu.ledc_clk.modify(|x| x.enable_clock_gating());
+        p.gpio.pc0.into_function::<4>();
+    }
+
+    let ledc = p.ledc;
+    unsafe {
+        // Soft reset LDEC
+        ledc.ledc_control.modify(|x| x.clear_soft_reset());
+        // Wait reset done
+        while ledc.ledc_control.read().soft_reset() {
+            core::hint::spin_loop();
+        }
+    }
+
+    const STEPS: [u8; 3] = [1, 2, 3];
+    let mut color = [0, 0, 0];
+
+    let wrap_color = |input: u32, flag: bool| {
+        if flag { 255 - input } else { input }
+    };
+    let color_to_u32 = |color: &[u32; 3]| {
+        let green = wrap_color(color[0] & 0xff, ((color[0] & 0x100) >> 8) == 0);
+        let red = wrap_color(color[1] & 0xff, ((color[1] & 0x100) >> 8) == 0);
+        let blue = wrap_color(color[2] & 0xff, ((color[2] & 0x100) >> 8) == 0);
+        (green << 16) | (red << 8) | blue
+    };
+
+    loop {
+        unsafe {
+            // Soft reset LDEC
+            ledc.ledc_control.modify(|x| x.clear_soft_reset());
+            // Wait reset done
+            while ledc.ledc_control.read().soft_reset() {
+                core::hint::spin_loop();
+            }
+
+            ledc.ledc_data_reg.write(color_to_u32(&color));
+
+            // Send on data
+            ledc.ledc_control
+                .modify(|x| x.set_total_data_length(1).enable());
+
+            while ledc.ledc_control.read().is_enabled() {
+                core::hint::spin_loop();
+            }
+
+            sleep(10);
+            for i in 0..3 {
+                color[i] += STEPS[i] as u32;
+            }
+        }
+    }
 }