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refactor: migrate allwinner-hal project to Rust edition 2024
Signed-off-by: Zhouqi Jiang <[email protected]>
1 parent 5549e07 commit e1c8317

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6 files changed

+146
-92
lines changed

6 files changed

+146
-92
lines changed

‎Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,6 @@ members = [
1010
]
1111

1212
[workspace.package]
13-
edition = "2021"
13+
edition = "2024"
1414
license = "MulanPSL-2.0 OR MIT"
1515
repository = "https://github.com/rustsbi/allwinner-hal"

‎allwinner-hal/src/ccu.rs

Lines changed: 107 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -529,15 +529,19 @@ pub trait ClockGate: ClockReset {
529529
/// Reset this peripheral without reconfiguring clocks (if applicable).
530530
#[inline]
531531
unsafe fn reset(ccu: &RegisterBlock) {
532-
// assert reset and then deassert reset.
533-
Self::disable_in(ccu);
534-
Self::enable_in(ccu);
532+
unsafe {
533+
// assert reset and then deassert reset.
534+
Self::disable_in(ccu);
535+
Self::enable_in(ccu);
536+
}
535537
}
536538
/// Free this peripheral by provided `ccu`.
537539
#[inline]
538540
unsafe fn free(ccu: &RegisterBlock) {
539-
// by default, asserting reset signal and mask clock gate.
540-
Self::disable_in(ccu);
541+
unsafe {
542+
// by default, asserting reset signal and mask clock gate.
543+
Self::disable_in(ccu);
544+
}
541545
}
542546
}
543547

@@ -564,9 +568,11 @@ pub trait ClockConfig {
564568
) where
565569
Self: ClockGate,
566570
{
567-
Self::disable_in(ccu);
568-
Self::configure(ccu, source, factor_m, factor_n);
569-
Self::enable_in(ccu);
571+
unsafe {
572+
Self::disable_in(ccu);
573+
Self::configure(ccu, source, factor_m, factor_n);
574+
Self::enable_in(ccu);
575+
}
570576
}
571577
/// Reconfigure this clock with dependency to a resettable clock type `T`.
572578
#[inline]
@@ -580,15 +586,17 @@ pub trait ClockConfig {
580586
F: FnOnce(&RegisterBlock) -> (Self::Source, u8, PeriFactorN),
581587
G: FnOnce(&RegisterBlock),
582588
{
583-
let _ = dependency; // does not use value, the type T is used instead
584-
T::assert_reset_only(ccu);
585-
Self::disable_in(ccu);
586-
let (source, factor_m, factor_n) = before_configure(ccu);
587-
Self::configure(ccu, source, factor_m, factor_n);
588-
after_configure(ccu);
589-
Self::deassert_reset_only(ccu);
590-
T::deassert_reset_only(ccu);
591-
Self::unmask_gate_only(ccu);
589+
unsafe {
590+
let _ = dependency; // does not use value, the type T is used instead
591+
T::assert_reset_only(ccu);
592+
Self::disable_in(ccu);
593+
let (source, factor_m, factor_n) = before_configure(ccu);
594+
Self::configure(ccu, source, factor_m, factor_n);
595+
after_configure(ccu);
596+
Self::deassert_reset_only(ccu);
597+
T::deassert_reset_only(ccu);
598+
Self::unmask_gate_only(ccu);
599+
}
592600
}
593601
}
594602

@@ -600,30 +608,42 @@ pub struct DRAM;
600608
impl ClockReset for DRAM {
601609
#[inline]
602610
unsafe fn deassert_reset_only(ccu: &RegisterBlock) {
603-
ccu.dram_bgr.modify(|v| v.deassert_reset());
611+
unsafe {
612+
ccu.dram_bgr.modify(|v| v.deassert_reset());
613+
}
604614
}
605615
#[inline]
606616
unsafe fn assert_reset_only(ccu: &RegisterBlock) {
607-
ccu.dram_bgr.modify(|v| v.assert_reset());
617+
unsafe {
618+
ccu.dram_bgr.modify(|v| v.assert_reset());
619+
}
608620
}
609621
}
610622

611623
impl ClockGate for DRAM {
612624
#[inline]
613625
unsafe fn unmask_gate_only(ccu: &RegisterBlock) {
614-
ccu.dram_bgr.modify(|v| v.gate_pass());
626+
unsafe {
627+
ccu.dram_bgr.modify(|v| v.gate_pass());
628+
}
615629
}
616630
#[inline]
617631
unsafe fn mask_gate_only(ccu: &RegisterBlock) {
618-
ccu.dram_bgr.modify(|v| v.gate_mask());
632+
unsafe {
633+
ccu.dram_bgr.modify(|v| v.gate_mask());
634+
}
619635
}
620636
#[inline]
621637
unsafe fn disable_in(ccu: &RegisterBlock) {
622-
ccu.dram_bgr.modify(|v| v.gate_mask().assert_reset());
638+
unsafe {
639+
ccu.dram_bgr.modify(|v| v.gate_mask().assert_reset());
640+
}
623641
}
624642
#[inline]
625643
unsafe fn enable_in(ccu: &RegisterBlock) {
626-
ccu.dram_bgr.modify(|v| v.gate_pass().deassert_reset());
644+
unsafe {
645+
ccu.dram_bgr.modify(|v| v.gate_pass().deassert_reset());
646+
}
627647
}
628648
}
629649

@@ -637,13 +657,15 @@ impl ClockConfig for DRAM {
637657
factor_m: u8,
638658
factor_n: PeriFactorN,
639659
) {
640-
let dram_clk = ccu.dram_clock.read();
641-
ccu.dram_clock.write(
642-
dram_clk
643-
.set_clock_source(source)
644-
.set_factor_m(factor_m)
645-
.set_factor_n(factor_n),
646-
)
660+
unsafe {
661+
let dram_clk = ccu.dram_clock.read();
662+
ccu.dram_clock.write(
663+
dram_clk
664+
.set_clock_source(source)
665+
.set_factor_m(factor_m)
666+
.set_factor_n(factor_n),
667+
)
668+
}
647669
}
648670
}
649671

@@ -653,11 +675,15 @@ pub struct MBUS;
653675
impl ClockReset for MBUS {
654676
#[inline]
655677
unsafe fn assert_reset_only(ccu: &RegisterBlock) {
656-
ccu.mbus_clock.modify(|v| v.assert_reset());
678+
unsafe {
679+
ccu.mbus_clock.modify(|v| v.assert_reset());
680+
}
657681
}
658682
#[inline]
659683
unsafe fn deassert_reset_only(ccu: &RegisterBlock) {
660-
ccu.mbus_clock.modify(|v| v.deassert_reset());
684+
unsafe {
685+
ccu.mbus_clock.modify(|v| v.deassert_reset());
686+
}
661687
}
662688
}
663689

@@ -670,32 +696,44 @@ pub struct UART<const IDX: usize>;
670696
impl<const I: usize> ClockReset for UART<I> {
671697
#[inline]
672698
unsafe fn assert_reset_only(ccu: &RegisterBlock) {
673-
ccu.uart_bgr.modify(|v| v.assert_reset::<I>());
699+
unsafe {
700+
ccu.uart_bgr.modify(|v| v.assert_reset::<I>());
701+
}
674702
}
675703
#[inline]
676704
unsafe fn deassert_reset_only(ccu: &RegisterBlock) {
677-
ccu.uart_bgr.modify(|v| v.deassert_reset::<I>());
705+
unsafe {
706+
ccu.uart_bgr.modify(|v| v.deassert_reset::<I>());
707+
}
678708
}
679709
}
680710

681711
impl<const I: usize> ClockGate for UART<I> {
682712
#[inline]
683713
unsafe fn unmask_gate_only(ccu: &RegisterBlock) {
684-
ccu.uart_bgr.modify(|v| v.gate_pass::<I>());
714+
unsafe {
715+
ccu.uart_bgr.modify(|v| v.gate_pass::<I>());
716+
}
685717
}
686718
#[inline]
687719
unsafe fn mask_gate_only(ccu: &RegisterBlock) {
688-
ccu.uart_bgr.modify(|v| v.gate_mask::<I>());
720+
unsafe {
721+
ccu.uart_bgr.modify(|v| v.gate_mask::<I>());
722+
}
689723
}
690724
#[inline]
691725
unsafe fn disable_in(ccu: &RegisterBlock) {
692-
ccu.uart_bgr
693-
.modify(|v| v.gate_mask::<I>().assert_reset::<I>());
726+
unsafe {
727+
ccu.uart_bgr
728+
.modify(|v| v.gate_mask::<I>().assert_reset::<I>());
729+
}
694730
}
695731
#[inline]
696732
unsafe fn enable_in(ccu: &RegisterBlock) {
697-
ccu.uart_bgr
698-
.modify(|v| v.gate_pass::<I>().deassert_reset::<I>());
733+
unsafe {
734+
ccu.uart_bgr
735+
.modify(|v| v.gate_pass::<I>().deassert_reset::<I>());
736+
}
699737
}
700738
}
701739

@@ -706,32 +744,44 @@ pub struct SPI<const IDX: usize>;
706744
impl<const I: usize> ClockReset for SPI<I> {
707745
#[inline]
708746
unsafe fn assert_reset_only(ccu: &RegisterBlock) {
709-
ccu.spi_bgr.modify(|v| v.assert_reset::<I>());
747+
unsafe {
748+
ccu.spi_bgr.modify(|v| v.assert_reset::<I>());
749+
}
710750
}
711751
#[inline]
712752
unsafe fn deassert_reset_only(ccu: &RegisterBlock) {
713-
ccu.spi_bgr.modify(|v| v.deassert_reset::<I>());
753+
unsafe {
754+
ccu.spi_bgr.modify(|v| v.deassert_reset::<I>());
755+
}
714756
}
715757
}
716758

717759
impl<const I: usize> ClockGate for SPI<I> {
718760
#[inline]
719761
unsafe fn unmask_gate_only(ccu: &RegisterBlock) {
720-
ccu.spi_bgr.modify(|v| v.gate_pass::<I>());
762+
unsafe {
763+
ccu.spi_bgr.modify(|v| v.gate_pass::<I>());
764+
}
721765
}
722766
#[inline]
723767
unsafe fn mask_gate_only(ccu: &RegisterBlock) {
724-
ccu.spi_bgr.modify(|v| v.gate_mask::<I>());
768+
unsafe {
769+
ccu.spi_bgr.modify(|v| v.gate_mask::<I>());
770+
}
725771
}
726772
#[inline]
727773
unsafe fn disable_in(ccu: &RegisterBlock) {
728-
ccu.spi_bgr
729-
.modify(|v| v.gate_mask::<I>().assert_reset::<I>());
774+
unsafe {
775+
ccu.spi_bgr
776+
.modify(|v| v.gate_mask::<I>().assert_reset::<I>());
777+
}
730778
}
731779
#[inline]
732780
unsafe fn enable_in(ccu: &RegisterBlock) {
733-
ccu.spi_bgr
734-
.modify(|v| v.gate_pass::<I>().deassert_reset::<I>());
781+
unsafe {
782+
ccu.spi_bgr
783+
.modify(|v| v.gate_pass::<I>().deassert_reset::<I>());
784+
}
735785
}
736786
}
737787

@@ -744,13 +794,15 @@ impl<const I: usize> ClockConfig for SPI<I> {
744794
factor_m: u8,
745795
factor_n: PeriFactorN,
746796
) {
747-
let spi_clk = ccu.spi_clk[I].read();
748-
ccu.spi_clk[I].write(
749-
spi_clk
750-
.set_clock_source(source)
751-
.set_factor_m(factor_m)
752-
.set_factor_n(factor_n),
753-
)
797+
unsafe {
798+
let spi_clk = ccu.spi_clk[I].read();
799+
ccu.spi_clk[I].write(
800+
spi_clk
801+
.set_clock_source(source)
802+
.set_factor_m(factor_m)
803+
.set_factor_n(factor_n),
804+
)
805+
}
754806
}
755807
}
756808

‎allwinner-hal/src/gpio.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ pub use register::{Eint, PioPow, Port, RegisterBlock};
1616

1717
#[allow(unused)]
1818
macro_rules! impl_gpio_pins {
19-
($($px: ident:($P: expr, $N: expr, $M: ident);)+) => {
19+
($($px: ident:($P: expr_2021, $N: expr_2021, $M: ident);)+) => {
2020
/// GPIO pads in current platform.
2121
pub struct Pads<'a> {
2222
$(

‎allwinner-hal/src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ pub mod prelude {
3030

3131
#[allow(unused)]
3232
macro_rules! impl_pins_trait {
33-
($(($p: expr, $i: expr, $f: expr): $Trait: ty;)+) => {
33+
($(($p: expr_2021, $i: expr_2021, $f: expr_2021): $Trait: ty;)+) => {
3434
$(
3535
impl<'a> $Trait for $crate::gpio::Function<'a, $p, $i, $f> {}
3636
)+

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