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[AArch64] Fix the type of NZCV operands/results
Consistently use `FlagsVT` for operands/results of nodes that consume/produce NZCV flags. Previously, some of the operands/results had incorrect `MVT::Glue` type while others had `MVT_CC` type, which is supposed to be used for condition codes (`AArch64CC::CondCode` enum). Found by llvm#150125.
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7 files changed

+81
-68
lines changed

7 files changed

+81
-68
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 27 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,9 @@ static cl::opt<bool> UseFEATCPACodegen(
164164
/// Value type used for condition codes.
165165
static const MVT MVT_CC = MVT::i32;
166166

167+
/// Value type used for NZCV flags.
168+
static constexpr MVT FlagsVT = MVT::i32;
169+
167170
static const MCPhysReg GPRArgRegs[] = {AArch64::X0, AArch64::X1, AArch64::X2,
168171
AArch64::X3, AArch64::X4, AArch64::X5,
169172
AArch64::X6, AArch64::X7};
@@ -3451,7 +3454,7 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &DL,
34513454
}
34523455
unsigned Opcode =
34533456
IsSignaling ? AArch64ISD::STRICT_FCMPE : AArch64ISD::STRICT_FCMP;
3454-
return DAG.getNode(Opcode, DL, {MVT::i32, MVT::Other}, {Chain, LHS, RHS});
3457+
return DAG.getNode(Opcode, DL, {FlagsVT, MVT::Other}, {Chain, LHS, RHS});
34553458
}
34563459

34573460
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
@@ -3465,7 +3468,7 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
34653468
LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
34663469
RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
34673470
}
3468-
return DAG.getNode(AArch64ISD::FCMP, DL, MVT::i32, LHS, RHS);
3471+
return DAG.getNode(AArch64ISD::FCMP, DL, FlagsVT, LHS, RHS);
34693472
}
34703473

34713474
// The CMP instruction is just an alias for SUBS, and representing it as
@@ -3490,7 +3493,7 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
34903493
// (a.k.a. ANDS) except that the flags are only guaranteed to work for one
34913494
// of the signed comparisons.
34923495
const SDValue ANDSNode =
3493-
DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(VT, MVT_CC),
3496+
DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(VT, FlagsVT),
34943497
LHS.getOperand(0), LHS.getOperand(1));
34953498
// Replace all users of (and X, Y) with newly generated (ands X, Y)
34963499
DAG.ReplaceAllUsesWith(LHS, ANDSNode);
@@ -3501,7 +3504,7 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
35013504
}
35023505
}
35033506

3504-
return DAG.getNode(Opcode, DL, DAG.getVTList(VT, MVT_CC), LHS, RHS)
3507+
return DAG.getNode(Opcode, DL, DAG.getVTList(VT, FlagsVT), LHS, RHS)
35053508
.getValue(1);
35063509
}
35073510

@@ -3597,7 +3600,7 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
35973600
AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
35983601
unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
35993602
SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
3600-
return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
3603+
return DAG.getNode(Opcode, DL, FlagsVT, LHS, RHS, NZCVOp, Condition, CCOp);
36013604
}
36023605

36033606
/// Returns true if @p Val is a tree of AND/OR/SETCC operations that can be
@@ -4036,7 +4039,7 @@ getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
40364039
Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
40374040

40384041
// Check that the result fits into a 32-bit integer.
4039-
SDVTList VTs = DAG.getVTList(MVT::i64, MVT_CC);
4042+
SDVTList VTs = DAG.getVTList(MVT::i64, FlagsVT);
40404043
if (IsSigned) {
40414044
// cmp xreg, wreg, sxtw
40424045
SDValue SExtMul = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Value);
@@ -4059,12 +4062,12 @@ getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
40594062
DAG.getConstant(63, DL, MVT::i64));
40604063
// It is important that LowerBits is last, otherwise the arithmetic
40614064
// shift will not be folded into the compare (SUBS).
4062-
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
4065+
SDVTList VTs = DAG.getVTList(MVT::i64, FlagsVT);
40634066
Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
40644067
.getValue(1);
40654068
} else {
40664069
SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
4067-
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
4070+
SDVTList VTs = DAG.getVTList(MVT::i64, FlagsVT);
40684071
Overflow =
40694072
DAG.getNode(AArch64ISD::SUBS, DL, VTs,
40704073
DAG.getConstant(0, DL, MVT::i64),
@@ -4075,7 +4078,7 @@ getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
40754078
} // switch (...)
40764079

40774080
if (Opc) {
4078-
SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
4081+
SDVTList VTs = DAG.getVTList(Op->getValueType(0), FlagsVT);
40794082

40804083
// Emit the AArch64 operation with overflow check.
40814084
Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
@@ -4177,7 +4180,7 @@ static SDValue valueToCarryFlag(SDValue Value, SelectionDAG &DAG, bool Invert) {
41774180
SDValue Op0 = Invert ? DAG.getConstant(0, DL, VT) : Value;
41784181
SDValue Op1 = Invert ? Value : DAG.getConstant(1, DL, VT);
41794182
SDValue Cmp =
4180-
DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::Glue), Op0, Op1);
4183+
DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, FlagsVT), Op0, Op1);
41814184
return Cmp.getValue(1);
41824185
}
41834186

@@ -4222,7 +4225,7 @@ static SDValue lowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG,
42224225
SDLoc DL(Op);
42234226
SDVTList VTs = DAG.getVTList(VT0, VT1);
42244227

4225-
SDValue Sum = DAG.getNode(Opcode, DL, DAG.getVTList(VT0, MVT::Glue), OpLHS,
4228+
SDValue Sum = DAG.getNode(Opcode, DL, DAG.getVTList(VT0, FlagsVT), OpLHS,
42264229
OpRHS, OpCarryIn);
42274230

42284231
SDValue OutFlag =
@@ -7037,9 +7040,8 @@ SDValue AArch64TargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
70377040
SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
70387041
Op.getOperand(0));
70397042
// Generate SUBS & CSEL.
7040-
SDValue Cmp =
7041-
DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
7042-
Op.getOperand(0), DAG.getConstant(0, DL, VT));
7043+
SDValue Cmp = DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, FlagsVT),
7044+
Op.getOperand(0), DAG.getConstant(0, DL, VT));
70437045
return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg,
70447046
DAG.getConstant(AArch64CC::PL, DL, MVT::i32),
70457047
Cmp.getValue(1));
@@ -11108,7 +11110,7 @@ SDValue AArch64TargetLowering::LowerSETCCCARRY(SDValue Op,
1110811110
SDValue Carry = Op.getOperand(2);
1110911111
// SBCS uses a carry not a borrow so the carry flag should be inverted first.
1111011112
SDValue InvCarry = valueToCarryFlag(Carry, DAG, true);
11111-
SDValue Cmp = DAG.getNode(AArch64ISD::SBCS, DL, DAG.getVTList(VT, MVT::Glue),
11113+
SDValue Cmp = DAG.getNode(AArch64ISD::SBCS, DL, DAG.getVTList(VT, FlagsVT),
1111211114
LHS, RHS, InvCarry);
1111311115

1111411116
EVT OpVT = Op.getValueType();
@@ -12441,10 +12443,10 @@ SDValue AArch64TargetLowering::LowerAsmOutputForConstraint(
1244112443

1244212444
// Get NZCV register. Only update chain when copyfrom is glued.
1244312445
if (Glue.getNode()) {
12444-
Glue = DAG.getCopyFromReg(Chain, DL, AArch64::NZCV, MVT::i32, Glue);
12446+
Glue = DAG.getCopyFromReg(Chain, DL, AArch64::NZCV, FlagsVT, Glue);
1244512447
Chain = Glue.getValue(1);
1244612448
} else
12447-
Glue = DAG.getCopyFromReg(Chain, DL, AArch64::NZCV, MVT::i32);
12449+
Glue = DAG.getCopyFromReg(Chain, DL, AArch64::NZCV, FlagsVT);
1244812450
// Extract CC code.
1244912451
SDValue CC = getSETCC(Cond, Glue, DL, DAG);
1245012452

@@ -18593,7 +18595,7 @@ AArch64TargetLowering::BuildSREMPow2(SDNode *N, const APInt &Divisor,
1859318595
Created.push_back(And.getNode());
1859418596
} else {
1859518597
SDValue CCVal = DAG.getConstant(AArch64CC::MI, DL, MVT_CC);
18596-
SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18598+
SDVTList VTs = DAG.getVTList(VT, FlagsVT);
1859718599

1859818600
SDValue Negs = DAG.getNode(AArch64ISD::SUBS, DL, VTs, Zero, N0);
1859918601
SDValue AndPos = DAG.getNode(ISD::AND, DL, VT, N0, Pow2MinusOne);
@@ -19482,10 +19484,10 @@ static SDValue performANDORCSELCombine(SDNode *N, SelectionDAG &DAG) {
1948219484
// can select to CCMN to avoid the extra mov
1948319485
SDValue AbsOp1 =
1948419486
DAG.getConstant(Op1->getAPIntValue().abs(), DL, Op1->getValueType(0));
19485-
CCmp = DAG.getNode(AArch64ISD::CCMN, DL, MVT_CC, Cmp1.getOperand(0), AbsOp1,
19486-
NZCVOp, Condition, Cmp0);
19487+
CCmp = DAG.getNode(AArch64ISD::CCMN, DL, FlagsVT, Cmp1.getOperand(0),
19488+
AbsOp1, NZCVOp, Condition, Cmp0);
1948719489
} else {
19488-
CCmp = DAG.getNode(AArch64ISD::CCMP, DL, MVT_CC, Cmp1.getOperand(0),
19490+
CCmp = DAG.getNode(AArch64ISD::CCMP, DL, FlagsVT, Cmp1.getOperand(0),
1948919491
Cmp1.getOperand(1), NZCVOp, Condition, Cmp0);
1949019492
}
1949119493
return DAG.getNode(AArch64ISD::CSEL, DL, VT, CSel0.getOperand(0),
@@ -25134,8 +25136,9 @@ static SDValue reassociateCSELOperandsForCSE(SDNode *N, SelectionDAG &DAG) {
2513425136
if (!TReassocOp && !FReassocOp)
2513525137
return SDValue();
2513625138

25137-
SDValue NewCmp = DAG.getNode(AArch64ISD::SUBS, SDLoc(SubsNode),
25138-
DAG.getVTList(VT, MVT_CC), CmpOpOther, SubsOp);
25139+
SDValue NewCmp =
25140+
DAG.getNode(AArch64ISD::SUBS, SDLoc(SubsNode),
25141+
DAG.getVTList(VT, FlagsVT), CmpOpOther, SubsOp);
2513925142

2514025143
auto Reassociate = [&](SDValue ReassocOp, unsigned OpNum) {
2514125144
if (!ReassocOp)
@@ -27161,7 +27164,7 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2716127164
: AArch64SysReg::RNDRRS);
2716227165
SDLoc DL(N);
2716327166
SDValue A = DAG.getNode(
27164-
AArch64ISD::MRS, DL, DAG.getVTList(MVT::i64, MVT::i32, MVT::Other),
27167+
AArch64ISD::MRS, DL, DAG.getVTList(MVT::i64, FlagsVT, MVT::Other),
2716527168
N->getOperand(0), DAG.getConstant(Register, DL, MVT::i32));
2716627169
SDValue B = DAG.getNode(
2716727170
AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32),

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -430,26 +430,27 @@ def UseWzrToVecMove : Predicate<"Subtarget->useWzrToVecMove()">;
430430
def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
431431
[SDTCisSameAs<0, 2>,
432432
SDTCisSameAs<0, 3>,
433-
SDTCisInt<0>, SDTCisVT<1, i32>]>;
433+
SDTCisInt<0>,
434+
SDTCisVT<1, FlagsVT>]>;
434435

435436
// SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
436437
def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
437438
[SDTCisSameAs<0, 1>,
438439
SDTCisSameAs<0, 2>,
439440
SDTCisInt<0>,
440-
SDTCisVT<3, i32>]>;
441+
SDTCisVT<3, FlagsVT>]>;
441442

442443
// SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
443444
def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
444445
[SDTCisSameAs<0, 2>,
445446
SDTCisSameAs<0, 3>,
446447
SDTCisInt<0>,
447-
SDTCisVT<1, i32>,
448-
SDTCisVT<4, i32>]>;
448+
SDTCisVT<1, FlagsVT>,
449+
SDTCisVT<4, FlagsVT>]>;
449450

450451
def SDT_AArch64Brcond : SDTypeProfile<0, 3,
451452
[SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
452-
SDTCisVT<2, i32>]>;
453+
SDTCisVT<2, FlagsVT>]>;
453454
def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
454455
def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
455456
SDTCisVT<2, OtherVT>]>;
@@ -458,22 +459,22 @@ def SDT_AArch64CSel : SDTypeProfile<1, 4,
458459
[SDTCisSameAs<0, 1>,
459460
SDTCisSameAs<0, 2>,
460461
SDTCisInt<3>,
461-
SDTCisVT<4, i32>]>;
462+
SDTCisVT<4, FlagsVT>]>;
462463
def SDT_AArch64CCMP : SDTypeProfile<1, 5,
463-
[SDTCisVT<0, i32>,
464+
[SDTCisVT<0, FlagsVT>,
464465
SDTCisInt<1>,
465466
SDTCisSameAs<1, 2>,
466467
SDTCisInt<3>,
467468
SDTCisInt<4>,
468469
SDTCisVT<5, i32>]>;
469470
def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
470-
[SDTCisVT<0, i32>,
471+
[SDTCisVT<0, FlagsVT>,
471472
SDTCisFP<1>,
472473
SDTCisSameAs<1, 2>,
473474
SDTCisInt<3>,
474475
SDTCisInt<4>,
475476
SDTCisVT<5, i32>]>;
476-
def SDT_AArch64FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
477+
def SDT_AArch64FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, FlagsVT>,
477478
SDTCisFP<1>,
478479
SDTCisSameAs<2, 1>]>;
479480
def SDT_AArch64Rev : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>]>;
@@ -1124,10 +1125,10 @@ def AArch64probedalloca
11241125
SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
11251126
[SDNPHasChain, SDNPMayStore]>;
11261127

1127-
// MRS, also sets the flags via a glue.
1128+
// MRS, also sets the flags.
11281129
def AArch64mrs : SDNode<"AArch64ISD::MRS",
11291130
SDTypeProfile<2, 1, [SDTCisVT<0, i64>,
1130-
SDTCisVT<1, i32>,
1131+
SDTCisVT<1, FlagsVT>,
11311132
SDTCisVT<2, i32>]>,
11321133
[SDNPHasChain]>;
11331134

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -305,7 +305,8 @@ def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">;
305305
def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">;
306306

307307
// Condition code regclass.
308-
def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
308+
defvar FlagsVT = i32;
309+
def CCR : RegisterClass<"AArch64", [FlagsVT], 32, (add NZCV)> {
309310
let CopyCost = -1; // Don't allow copying of status registers.
310311

311312
// CCR is not allocatable.

‎llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp‎

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,10 +32,29 @@ AArch64SelectionDAGInfo::AArch64SelectionDAGInfo()
3232

3333
void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
3434
const SDNode *N) const {
35+
SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
36+
3537
#ifndef NDEBUG
38+
// Some additional checks not yet implemented by verifyTargetNode.
39+
constexpr MVT FlagsVT = MVT::i32;
3640
switch (N->getOpcode()) {
37-
default:
38-
return SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
41+
case AArch64ISD::SUBS:
42+
assert(N->getValueType(1) == FlagsVT);
43+
break;
44+
case AArch64ISD::ADC:
45+
case AArch64ISD::SBC:
46+
assert(N->getOperand(2).getValueType() == FlagsVT);
47+
break;
48+
case AArch64ISD::ADCS:
49+
case AArch64ISD::SBCS:
50+
assert(N->getValueType(1) == FlagsVT);
51+
assert(N->getOperand(2).getValueType() == FlagsVT);
52+
break;
53+
case AArch64ISD::CSEL:
54+
case AArch64ISD::CSINC:
55+
case AArch64ISD::BRCOND:
56+
assert(N->getOperand(3).getValueType() == FlagsVT);
57+
break;
3958
case AArch64ISD::SADDWT:
4059
case AArch64ISD::SADDWB:
4160
case AArch64ISD::UADDWT:

‎llvm/test/CodeGen/AArch64/abds-neg.ll‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -200,8 +200,7 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
200200
; CHECK-NEXT: subs x8, x0, x2
201201
; CHECK-NEXT: sbc x9, x1, x3
202202
; CHECK-NEXT: subs x10, x2, x0
203-
; CHECK-NEXT: sbc x11, x3, x1
204-
; CHECK-NEXT: sbcs xzr, x3, x1
203+
; CHECK-NEXT: sbcs x11, x3, x1
205204
; CHECK-NEXT: csel x8, x8, x10, lt
206205
; CHECK-NEXT: csel x9, x9, x11, lt
207206
; CHECK-NEXT: negs x0, x8
@@ -222,8 +221,7 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
222221
; CHECK-NEXT: subs x8, x0, x2
223222
; CHECK-NEXT: sbc x9, x1, x3
224223
; CHECK-NEXT: subs x10, x2, x0
225-
; CHECK-NEXT: sbc x11, x3, x1
226-
; CHECK-NEXT: sbcs xzr, x3, x1
224+
; CHECK-NEXT: sbcs x11, x3, x1
227225
; CHECK-NEXT: csel x8, x8, x10, lt
228226
; CHECK-NEXT: csel x9, x9, x11, lt
229227
; CHECK-NEXT: negs x0, x8
@@ -389,14 +387,12 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
389387
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
390388
; CHECK-LABEL: abd_cmp_i128:
391389
; CHECK: // %bb.0:
392-
; CHECK-NEXT: cmp x0, x2
393-
; CHECK-NEXT: sbc x8, x1, x3
394-
; CHECK-NEXT: subs x9, x2, x0
395-
; CHECK-NEXT: sbc x10, x3, x1
396-
; CHECK-NEXT: subs x11, x0, x2
397-
; CHECK-NEXT: sbcs xzr, x1, x3
398-
; CHECK-NEXT: csel x0, x11, x9, lt
399-
; CHECK-NEXT: csel x1, x8, x10, lt
390+
; CHECK-NEXT: subs x8, x2, x0
391+
; CHECK-NEXT: sbc x9, x3, x1
392+
; CHECK-NEXT: subs x10, x0, x2
393+
; CHECK-NEXT: sbcs x11, x1, x3
394+
; CHECK-NEXT: csel x0, x10, x8, lt
395+
; CHECK-NEXT: csel x1, x11, x9, lt
400396
; CHECK-NEXT: ret
401397
%cmp = icmp slt i128 %a, %b
402398
%ab = sub i128 %a, %b

‎llvm/test/CodeGen/AArch64/abds.ll‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -183,8 +183,7 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
183183
; CHECK-NEXT: subs x8, x0, x2
184184
; CHECK-NEXT: sbc x9, x1, x3
185185
; CHECK-NEXT: subs x10, x2, x0
186-
; CHECK-NEXT: sbc x11, x3, x1
187-
; CHECK-NEXT: sbcs xzr, x3, x1
186+
; CHECK-NEXT: sbcs x11, x3, x1
188187
; CHECK-NEXT: csel x0, x8, x10, lt
189188
; CHECK-NEXT: csel x1, x9, x11, lt
190189
; CHECK-NEXT: ret
@@ -202,8 +201,7 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
202201
; CHECK-NEXT: subs x8, x0, x2
203202
; CHECK-NEXT: sbc x9, x1, x3
204203
; CHECK-NEXT: subs x10, x2, x0
205-
; CHECK-NEXT: sbc x11, x3, x1
206-
; CHECK-NEXT: sbcs xzr, x3, x1
204+
; CHECK-NEXT: sbcs x11, x3, x1
207205
; CHECK-NEXT: csel x0, x8, x10, lt
208206
; CHECK-NEXT: csel x1, x9, x11, lt
209207
; CHECK-NEXT: ret
@@ -279,8 +277,7 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
279277
; CHECK-NEXT: subs x8, x0, x2
280278
; CHECK-NEXT: sbc x9, x1, x3
281279
; CHECK-NEXT: subs x10, x2, x0
282-
; CHECK-NEXT: sbc x11, x3, x1
283-
; CHECK-NEXT: sbcs xzr, x3, x1
280+
; CHECK-NEXT: sbcs x11, x3, x1
284281
; CHECK-NEXT: csel x0, x8, x10, lt
285282
; CHECK-NEXT: csel x1, x9, x11, lt
286283
; CHECK-NEXT: ret
@@ -358,8 +355,7 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
358355
; CHECK-NEXT: subs x8, x0, x2
359356
; CHECK-NEXT: sbc x9, x1, x3
360357
; CHECK-NEXT: subs x10, x2, x0
361-
; CHECK-NEXT: sbc x11, x3, x1
362-
; CHECK-NEXT: sbcs xzr, x3, x1
358+
; CHECK-NEXT: sbcs x11, x3, x1
363359
; CHECK-NEXT: csel x0, x8, x10, lt
364360
; CHECK-NEXT: csel x1, x9, x11, lt
365361
; CHECK-NEXT: ret
@@ -607,8 +603,7 @@ define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
607603
; CHECK-NEXT: subs x8, x0, x2
608604
; CHECK-NEXT: sbc x9, x1, x3
609605
; CHECK-NEXT: subs x10, x2, x0
610-
; CHECK-NEXT: sbc x11, x3, x1
611-
; CHECK-NEXT: sbcs xzr, x3, x1
606+
; CHECK-NEXT: sbcs x11, x3, x1
612607
; CHECK-NEXT: csel x0, x8, x10, lt
613608
; CHECK-NEXT: csel x1, x9, x11, lt
614609
; CHECK-NEXT: ret

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